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Try again to fix our handling of MOVD/MOVQ

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Try to implement the handling of MOVD as attempted in checkin:

    70712c0df6

and reverted in:

    d279fbbd80

due to BR3392199.  This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin 2012-03-05 22:37:21 -08:00
parent 9d91ff5b12
commit b106ba161f
2 changed files with 23 additions and 8 deletions
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16
insns.dat
View file

@ -834,14 +834,14 @@ MOV rm64,imm32 [mi: hlexr o64 c7 /0 idx] X64
MOV mem,imm8 [mi: hlexr c6 /0 ib] 8086,SM
MOV mem,imm16 [mi: hlexr o16 c7 /0 iw] 8086,SM
MOV mem,imm32 [mi: hlexr o32 c7 /0 id] 386,SM
MOVD mmxreg,rm32 [rm: np 0f 6e /r] PENT,MMX
MOVD rm32,mmxreg [mr: np 0f 7e /r] PENT,MMX
MOVD xmmreg,rm32 [rm: np o16 0f 6e /r] SSE2
MOVD rm32,xmmreg [mr: np o16 0f 7e /r] SSE2
MOVQ mmxreg,mmxrm [rm: np o64nw 0f 6f /r] PENT,MMX,SQ
MOVQ mmxrm,mmxreg [mr: np o64nw 0f 7f /r] PENT,MMX,SQ
MOVQ mmxreg,rm64 [rm: np 0f 6e /r] X64,MMX
MOVQ rm64,mmxreg [mr: np 0f 7e /r] X64,MMX
MOVD mmxreg,rm32 [rm: np 0f 6e /r] PENT,MMX,SD
MOVD rm32,mmxreg [mr: np 0f 7e /r] PENT,MMX,SD
MOVD mmxreg,rm64 [rm: np o64 0f 6e /r] X64,MMX,SX,ND
MOVD rm64,mmxreg [mr: np o64 0f 7e /r] X64,MMX,SX,ND
MOVQ mmxreg,mmxrm [rm: np 0f 6f /r] PENT,MMX,SQ
MOVQ mmxrm,mmxreg [mr: np 0f 7f /r] PENT,MMX,SQ
MOVQ mmxreg,rm64 [rm: np o64 0f 6e /r] X64,MMX
MOVQ rm64,mmxreg [mr: np o64 0f 7e /r] X64,MMX
MOVSB void [ a4] 8086
MOVSD void [ o32 a5] 386
MOVSQ void [ o64 a5] X64

15
test/movd64.asm Normal file
View file

@ -0,0 +1,15 @@
bits 64
movd r8d, mm1
movd r8, mm1
movq r8, mm1
movd [rax], mm1
movq [rax], mm1
movd dword [rax], mm1
; movq dword [rax], mm1
movd qword [rax], mm1
movq qword [rax], mm1
; movd mm2, mm1
movq mm2, mm1