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insns.dat: Mark the immediate for shift instructions as imm8

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Allow the form:

      mov <rm>,byte 1

... to generate the explicit byte form.  An unfortunate side effect is
that disassembly is ugly; this could be fixed by making a special byte
code that acts the same for the assembler but disassembles specially.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin 2012-09-25 22:51:40 -07:00
parent 7c6baca6d0
commit 5c72992a78
1 changed files with 32 additions and 32 deletions
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64
insns.dat
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@ -1051,28 +1051,28 @@ PUSHFW void [ o16 9c] 8086
PXOR mmxreg,mmxrm [rm: np o64nw 0f ef /r] PENT,MMX,SQ
RCL rm8,unity [m-: d0 /2] 8086
RCL rm8,reg_cl [m-: d2 /2] 8086
RCL rm8,imm [mi: c0 /2 ib,u] 186
RCL rm8,imm8 [mi: c0 /2 ib,u] 186
RCL rm16,unity [m-: o16 d1 /2] 8086
RCL rm16,reg_cl [m-: o16 d3 /2] 8086
RCL rm16,imm [mi: o16 c1 /2 ib,u] 186
RCL rm16,imm8 [mi: o16 c1 /2 ib,u] 186
RCL rm32,unity [m-: o32 d1 /2] 386
RCL rm32,reg_cl [m-: o32 d3 /2] 386
RCL rm32,imm [mi: o32 c1 /2 ib,u] 386
RCL rm32,imm8 [mi: o32 c1 /2 ib,u] 386
RCL rm64,unity [m-: o64 d1 /2] X64
RCL rm64,reg_cl [m-: o64 d3 /2] X64
RCL rm64,imm [mi: o64 c1 /2 ib,u] X64
RCL rm64,imm8 [mi: o64 c1 /2 ib,u] X64
RCR rm8,unity [m-: d0 /3] 8086
RCR rm8,reg_cl [m-: d2 /3] 8086
RCR rm8,imm [mi: c0 /3 ib,u] 186
RCR rm8,imm8 [mi: c0 /3 ib,u] 186
RCR rm16,unity [m-: o16 d1 /3] 8086
RCR rm16,reg_cl [m-: o16 d3 /3] 8086
RCR rm16,imm [mi: o16 c1 /3 ib,u] 186
RCR rm16,imm8 [mi: o16 c1 /3 ib,u] 186
RCR rm32,unity [m-: o32 d1 /3] 386
RCR rm32,reg_cl [m-: o32 d3 /3] 386
RCR rm32,imm [mi: o32 c1 /3 ib,u] 386
RCR rm32,imm8 [mi: o32 c1 /3 ib,u] 386
RCR rm64,unity [m-: o64 d1 /3] X64
RCR rm64,reg_cl [m-: o64 d3 /3] X64
RCR rm64,imm [mi: o64 c1 /3 ib,u] X64
RCR rm64,imm8 [mi: o64 c1 /3 ib,u] X64
RDSHR rm32 [m: o32 0f 36 /0] P6,CYRIX,SMM
RDMSR void [ 0f 32] PENT,PRIV
RDPMC void [ 0f 33] P6
@ -1086,28 +1086,28 @@ RETN void [ c3] 8086
RETN imm [i: c2 iw] 8086,SW
ROL rm8,unity [m-: d0 /0] 8086
ROL rm8,reg_cl [m-: d2 /0] 8086
ROL rm8,imm [mi: c0 /0 ib,u] 186
ROL rm8,imm8 [mi: c0 /0 ib,u] 186
ROL rm16,unity [m-: o16 d1 /0] 8086
ROL rm16,reg_cl [m-: o16 d3 /0] 8086
ROL rm16,imm [mi: o16 c1 /0 ib,u] 186
ROL rm16,imm8 [mi: o16 c1 /0 ib,u] 186
ROL rm32,unity [m-: o32 d1 /0] 386
ROL rm32,reg_cl [m-: o32 d3 /0] 386
ROL rm32,imm [mi: o32 c1 /0 ib,u] 386
ROL rm32,imm8 [mi: o32 c1 /0 ib,u] 386
ROL rm64,unity [m-: o64 d1 /0] X64
ROL rm64,reg_cl [m-: o64 d3 /0] X64
ROL rm64,imm [mi: o64 c1 /0 ib,u] X64
ROL rm64,imm8 [mi: o64 c1 /0 ib,u] X64
ROR rm8,unity [m-: d0 /1] 8086
ROR rm8,reg_cl [m-: d2 /1] 8086
ROR rm8,imm [mi: c0 /1 ib,u] 186
ROR rm8,imm8 [mi: c0 /1 ib,u] 186
ROR rm16,unity [m-: o16 d1 /1] 8086
ROR rm16,reg_cl [m-: o16 d3 /1] 8086
ROR rm16,imm [mi: o16 c1 /1 ib,u] 186
ROR rm16,imm8 [mi: o16 c1 /1 ib,u] 186
ROR rm32,unity [m-: o32 d1 /1] 386
ROR rm32,reg_cl [m-: o32 d3 /1] 386
ROR rm32,imm [mi: o32 c1 /1 ib,u] 386
ROR rm32,imm8 [mi: o32 c1 /1 ib,u] 386
ROR rm64,unity [m-: o64 d1 /1] X64
ROR rm64,reg_cl [m-: o64 d3 /1] X64
ROR rm64,imm [mi: o64 c1 /1 ib,u] X64
ROR rm64,imm8 [mi: o64 c1 /1 ib,u] X64
RDM void [ 0f 3a] P6,CYRIX,ND
RSDC reg_sreg,mem80 [rm: 0f 79 /r] 486,CYRIX,SMM
RSLDT mem80 [m: 0f 7b /0] 486,CYRIX,SMM
@ -1116,29 +1116,29 @@ RSTS mem80 [m: 0f 7d /0] 486,CYRIX,SMM
SAHF void [ 9e] 8086
SAL rm8,unity [m-: d0 /4] 8086,ND
SAL rm8,reg_cl [m-: d2 /4] 8086,ND
SAL rm8,imm [mi: c0 /4 ib,u] 186,ND
SAL rm8,imm8 [mi: c0 /4 ib,u] 186,ND
SAL rm16,unity [m-: o16 d1 /4] 8086,ND
SAL rm16,reg_cl [m-: o16 d3 /4] 8086,ND
SAL rm16,imm [mi: o16 c1 /4 ib,u] 186,ND
SAL rm16,imm8 [mi: o16 c1 /4 ib,u] 186,ND
SAL rm32,unity [m-: o32 d1 /4] 386,ND
SAL rm32,reg_cl [m-: o32 d3 /4] 386,ND
SAL rm32,imm [mi: o32 c1 /4 ib,u] 386,ND
SAL rm32,imm8 [mi: o32 c1 /4 ib,u] 386,ND
SAL rm64,unity [m-: o64 d1 /4] X64,ND
SAL rm64,reg_cl [m-: o64 d3 /4] X64,ND
SAL rm64,imm [mi: o64 c1 /4 ib,u] X64,ND
SAL rm64,imm8 [mi: o64 c1 /4 ib,u] X64,ND
SALC void [ d6] 8086,UNDOC
SAR rm8,unity [m-: d0 /7] 8086
SAR rm8,reg_cl [m-: d2 /7] 8086
SAR rm8,imm [mi: c0 /7 ib,u] 186
SAR rm8,imm8 [mi: c0 /7 ib,u] 186
SAR rm16,unity [m-: o16 d1 /7] 8086
SAR rm16,reg_cl [m-: o16 d3 /7] 8086
SAR rm16,imm [mi: o16 c1 /7 ib,u] 186
SAR rm16,imm8 [mi: o16 c1 /7 ib,u] 186
SAR rm32,unity [m-: o32 d1 /7] 386
SAR rm32,reg_cl [m-: o32 d3 /7] 386
SAR rm32,imm [mi: o32 c1 /7 ib,u] 386
SAR rm32,imm8 [mi: o32 c1 /7 ib,u] 386
SAR rm64,unity [m-: o64 d1 /7] X64
SAR rm64,reg_cl [m-: o64 d3 /7] X64
SAR rm64,imm [mi: o64 c1 /7 ib,u] X64
SAR rm64,imm8 [mi: o64 c1 /7 ib,u] X64
SBB mem,reg8 [mr: hle 18 /r] 8086,SM,LOCK
SBB reg8,reg8 [mr: 18 /r] 8086
SBB mem,reg16 [mr: hle o16 19 /r] 8086,SM,LOCK
@ -1181,16 +1181,16 @@ SFENCE void [ 0f ae f8] X64,AMD
SGDT mem [m: 0f 01 /0] 286
SHL rm8,unity [m-: d0 /4] 8086
SHL rm8,reg_cl [m-: d2 /4] 8086
SHL rm8,imm [mi: c0 /4 ib,u] 186
SHL rm8,imm8 [mi: c0 /4 ib,u] 186
SHL rm16,unity [m-: o16 d1 /4] 8086
SHL rm16,reg_cl [m-: o16 d3 /4] 8086
SHL rm16,imm [mi: o16 c1 /4 ib,u] 186
SHL rm16,imm8 [mi: o16 c1 /4 ib,u] 186
SHL rm32,unity [m-: o32 d1 /4] 386
SHL rm32,reg_cl [m-: o32 d3 /4] 386
SHL rm32,imm [mi: o32 c1 /4 ib,u] 386
SHL rm32,imm8 [mi: o32 c1 /4 ib,u] 386
SHL rm64,unity [m-: o64 d1 /4] X64
SHL rm64,reg_cl [m-: o64 d3 /4] X64
SHL rm64,imm [mi: o64 c1 /4 ib,u] X64
SHL rm64,imm8 [mi: o64 c1 /4 ib,u] X64
SHLD mem,reg16,imm [mri: o16 0f a4 /r ib,u] 386,SM2,SB,AR2
SHLD reg16,reg16,imm [mri: o16 0f a4 /r ib,u] 386,SM2,SB,AR2
SHLD mem,reg32,imm [mri: o32 0f a4 /r ib,u] 386,SM2,SB,AR2
@ -1205,16 +1205,16 @@ SHLD mem,reg64,reg_cl [mr-: o64 0f a5 /r] X64,SM
SHLD reg64,reg64,reg_cl [mr-: o64 0f a5 /r] X64
SHR rm8,unity [m-: d0 /5] 8086
SHR rm8,reg_cl [m-: d2 /5] 8086
SHR rm8,imm [mi: c0 /5 ib,u] 186
SHR rm8,imm8 [mi: c0 /5 ib,u] 186
SHR rm16,unity [m-: o16 d1 /5] 8086
SHR rm16,reg_cl [m-: o16 d3 /5] 8086
SHR rm16,imm [mi: o16 c1 /5 ib,u] 186
SHR rm16,imm8 [mi: o16 c1 /5 ib,u] 186
SHR rm32,unity [m-: o32 d1 /5] 386
SHR rm32,reg_cl [m-: o32 d3 /5] 386
SHR rm32,imm [mi: o32 c1 /5 ib,u] 386
SHR rm32,imm8 [mi: o32 c1 /5 ib,u] 386
SHR rm64,unity [m-: o64 d1 /5] X64
SHR rm64,reg_cl [m-: o64 d3 /5] X64
SHR rm64,imm [mi: o64 c1 /5 ib,u] X64
SHR rm64,imm8 [mi: o64 c1 /5 ib,u] X64
SHRD mem,reg16,imm [mri: o16 0f ac /r ib,u] 386,SM2,SB,AR2
SHRD reg16,reg16,imm [mri: o16 0f ac /r ib,u] 386,SM2,SB,AR2
SHRD mem,reg32,imm [mri: o32 0f ac /r ib,u] 386,SM2,SB,AR2