Clean up the existing operand flag definitions, and document
This commit is contained in:
H. Peter Anvin
parent
7a83374a9c
commit
5a640e1161
4 changed files with 138 additions and 66 deletions
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@ -1504,7 +1504,7 @@ static int matches(struct itemplate *itemp, insn * instruction, int bits)
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if (itemp->opd[i] & ~instruction->oprs[i].type ||
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((itemp->opd[i] & SIZE_MASK) &&
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((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
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if ((itemp->opd[i] & ~instruction->oprs[i].type & NON_SIZE) ||
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if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
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(instruction->oprs[i].type & SIZE_MASK))
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return 0;
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else
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2
disasm.c
2
disasm.c
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@ -472,7 +472,7 @@ static int matches(struct itemplate *t, uint8_t *data, int asize,
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}
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if (segsize != osize) {
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ins->oprs[c - 064].type =
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(ins->oprs[c - 064].type & NON_SIZE)
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(ins->oprs[c - 064].type & ~SIZE_MASK)
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| ((osize == 16) ? BITS16 : BITS32);
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}
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} else if (c >= 070 && c <= 072) {
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9
nasm.c
9
nasm.c
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@ -1123,10 +1123,11 @@ static void assemble_file(char *fname)
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*/
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if (output_ins.operands >= 2 &&
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(output_ins.oprs[1].opflags & OPFLAG_FORWARD))
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{
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output_ins.oprs[1].type &=
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~(ONENESS | BYTENESS);
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(output_ins.oprs[1].opflags & OPFLAG_FORWARD) &&
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!(IMMEDIATE & ~output_ins.oprs[1].type))
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{
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/* Remove special properties bits */
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output_ins.oprs[1].type &= ~REG_SMASK;
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}
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} /* pass == 2 */
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191
nasm.h
191
nasm.h
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@ -370,78 +370,149 @@ enum {
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* instruction is a special operand type, whereas AX in other
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* contexts is just another 16-bit register. (Also, consider CL in
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* shift instructions, DX in OUT, etc.)
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*
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* The basic concept here is that
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* (class & ~operand) == 0
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*
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* if and only if "operand" is of type "class".
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*
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* The bits are assigned as follows:
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*
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* Bits 0-7: sizes
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* 0: 8 bits (BYTE)
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* 1: 16 bits (WORD)
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* 2: 32 bits (DWORD)
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* 3: 64 bits (QWORD)
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* 4: 80 bits (TWORD)
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* 5: FAR
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* 6: NEAR
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* 7: SHORT
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*
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* Bits 8-11: modifiers
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* 8: TO
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* 9: COLON
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* 10: STRICT
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* 11: (reserved)
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*
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* Bits 12-15: type of operand
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* 12: REGISTER
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* 13: IMMEDIATE
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* 14: MEMORY (always has REGMEM attribute as well)
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* 15: (reserved)
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*
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* Bits 16-19: subclasses
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* With REG_CDT:
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* 16: REG_CREG (CRx)
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* 17: REG_DREG (DRx)
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* 18: REG_TREG (TRx)
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* With REGNORM == REGMEM|REGISTER:
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* 16: REG_ACCUM (AL, AX, EAX, RAX) or
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* 17: REG_COUNT (CL, CX, ECX, RCX)
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* 18: REG_DATA (DL, DX, EDX, RDX)
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*
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* With REG_SREG:
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* 16: REG_CS
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* 17: REG_DESS (DS, ES, SS)
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* 18: REG_FSGS
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* 19: REG_SEG67
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*
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* With FPUREG:
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* 16: FPU0
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*
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* With MEMORY:
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* 16: MEM_OFFS (this is a simple offset)
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*
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* With IMMEDIATE:
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* 16: UNITY (1)
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* 17: BYTENESS (-128..127)
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*
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* Bits 20-26: register classes
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* 20: REG_CDT (CRx, DRx, TRx)
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* 21: REGMEM (GPR or memory operand)
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* 22: REG_SREG
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* 23: IP_REG (RIP or EIP)
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* 24: FPUREG
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* 25: MMXREG
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* 26: XMMREG
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*
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* Bits 27-31 are currently unallocated.
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*/
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/* size, and other attributes, of the operand */
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#define BITS8 0x00000001L
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#define BITS16 0x00000002L
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#define BITS32 0x00000004L
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#define BITS64 0x00000008L /* x64 and FPU only */
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#define BITS80 0x00000010L /* FPU only */
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#define FAR 0x00000020L /* grotty: this means 16:16 or */
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/* Size, and other attributes, of the operand */
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#define BITS8 0x00000001L
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#define BITS16 0x00000002L
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#define BITS32 0x00000004L
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#define BITS64 0x00000008L /* x64 and FPU only */
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#define BITS80 0x00000010L /* FPU only */
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#define FAR 0x00000020L /* grotty: this means 16:16 or */
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/* 16:32, like in CALL/JMP */
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#define NEAR 0x00000040L
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#define SHORT 0x00000080L /* and this means what it says :) */
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#define NEAR 0x00000040L
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#define SHORT 0x00000080L /* and this means what it says :) */
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#define SIZE_MASK 0x000000FFL /* all the size attributes */
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#define NON_SIZE (~SIZE_MASK)
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#define SIZE_MASK 0x000000FFL /* all the size attributes */
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#define TO 0x00000100L /* reverse effect in FADD, FSUB &c */
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#define COLON 0x00000200L /* operand is followed by a colon */
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#define STRICT 0x00000400L /* do not optimize this operand */
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/* Modifiers */
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#define MODIFIER_MASK 0x00000f00L
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#define TO 0x00000100L /* reverse effect in FADD, FSUB &c */
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#define COLON 0x00000200L /* operand is followed by a colon */
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#define STRICT 0x00000400L /* do not optimize this operand */
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/* type of operand: memory reference, register, etc. */
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#define MEMORY 0x00204000L
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#define REGISTER 0x00001000L /* register number in 'basereg' */
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#define IMMEDIATE 0x00002000L
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/* Type of operand: memory reference, register, etc. */
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#define OPTYPE_MASK 0x0000f000L
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#define REGISTER 0x00001000L /* register number in 'basereg' */
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#define IMMEDIATE 0x00002000L
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#define MEMORY 0x00204000L
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#define REGMEM 0x00200000L /* for r/m, ie EA, operands */
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#define REGNORM 0x00201000L /* 'normal' reg, qualifies as EA */
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#define REG8 0x00201001L
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#define REG16 0x00201002L
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#define REG32 0x00201004L
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#define REG64 0x00201008L /* x64 registers */
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#define RIPREG 0x0020100CL /* RIP register */
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#define MMXREG 0x00201010L /* MMX registers */
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#define XMMREG 0x00201011L /* XMM Katmai reg */
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#define FPUREG 0x01000000L /* floating point stack registers */
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#define FPU0 0x01000800L /* FPU stack register zero */
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#define REGMEM 0x00200000L /* for r/m, ie EA, operands */
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#define REGNORM 0x00201000L /* 'normal' reg, qualifies as EA */
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#define REG8 0x00201001L
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#define REG16 0x00201002L
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#define REG32 0x00201004L
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#define REG64 0x00201008L
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#define IP_REG 0x00800000L /* RIP or EIP register */
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#define RIPREG 0x00800008L /* RIP */
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#define EIPREG 0x00800004L /* EIP */
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#define FPUREG 0x01000000L /* floating point stack registers */
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#define MMXREG 0x02000008L /* MMX registers */
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#define XMMREG 0x04000001L /* XMM Katmai reg */
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#define FPU0 0x01001000L /* FPU stack register zero */
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/* special register operands: these may be treated differently */
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#define REG_SMASK 0x00070000L /* a mask for the following */
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#define REG_ACCUM 0x00211000L /* accumulator: AL, AX or EAX */
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#define REG_AL 0x00211001L /* REG_ACCUM | BITSxx */
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#define REG_AX 0x00211002L /* ditto */
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#define REG_EAX 0x00211004L /* and again */
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#define REG_RAX 0x00211008L /* and again */
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#define REG_COUNT 0x00221000L /* counter: CL, CX, ECX or RCX */
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#define REG_CL 0x00221001L /* REG_COUNT | BITSxx */
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#define REG_CX 0x00221002L /* ditto */
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#define REG_ECX 0x00221004L /* another one */
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#define REG_RCX 0x00221008L /* another one */
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#define REG_DL 0x00241001L
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#define REG_DX 0x00241002L
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#define REG_EDX 0x00241004L
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#define REG_RDX 0x00241008L
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#define REG_RIP 0x0027100CL /* RIP relative addressing */
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#define REG_SREG 0x00081002L /* any segment register */
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#define REG_CS 0x01081002L /* CS */
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#define REG_DESS 0x02081002L /* DS, ES, SS (non-CS 86 registers) */
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#define REG_FSGS 0x04081002L /* FS, GS (386 extended registers) */
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#define REG_SEG67 0x08081002L /* Non-implemented segment registers */
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#define REG_CDT 0x00101004L /* CRn, DRn and TRn */
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#define REG_CREG 0x08101004L /* CRn */
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#define REG_DREG 0x10101004L /* DRn */
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#define REG_TREG 0x20101004L /* TRn */
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/* Special GPRs */
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#define REG_SMASK 0x000f0000L /* a mask for the following */
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#define REG_ACCUM 0x00211000L /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL 0x00211001L
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#define REG_AX 0x00211002L
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#define REG_EAX 0x00211004L
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#define REG_RAX 0x00211008L
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#define REG_COUNT 0x00221000L /* counter: CL, CX, ECX, RCX */
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#define REG_CL 0x00221001L
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#define REG_CX 0x00221002L
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#define REG_ECX 0x00221004L
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#define REG_RCX 0x00221008L
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#define REG_DL 0x00241001L /* data: DL, DX, EDX, RDX */
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#define REG_DX 0x00241002L
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#define REG_EDX 0x00241004L
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#define REG_RDX 0x00241008L
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#define REG_RIP 0x0027100CL /* RIP relative addressing */
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/* Register classes */
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#define REG_CDT 0x00101004L /* CRn, DRn and TRn */
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#define REG_CREG 0x00111004L /* CRn */
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#define REG_DREG 0x00121004L /* DRn */
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#define REG_TREG 0x00141004L /* TRn */
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#define REG_SREG 0x00401002L /* any segment register */
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#define REG_CS 0x00411002L /* CS */
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#define REG_DESS 0x00421002L /* DS, ES, SS */
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#define REG_FSGS 0x00441002L /* FS, GS */
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#define REG_SEG67 0x00481002L /* Unimplemented segment registers */
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/* special type of EA */
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#define MEM_OFFS 0x00604000L /* simple [address] offset */
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#define MEM_OFFS 0x00214000L /* simple [address] offset */
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/* special type of immediate operand */
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#define ONENESS 0x00800000L /* so UNITY == IMMEDIATE | ONENESS */
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#define UNITY 0x00802000L /* for shift/rotate instructions */
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#define BYTENESS 0x40000000L /* so SBYTE == IMMEDIATE | BYTENESS */
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#define SBYTE 0x40002000L /* for op r16/32,immediate instrs. */
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#define UNITY 0x00012000L /* for shift/rotate instructions */
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#define SBYTE 0x00022000L /* for op r16/32,immediate instrs. */
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/* Register names automatically generated from regs.dat */
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#include "regs.h"
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