Remove +s
It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat. In order to make this work I had to rename sbyte16/sbyte32 so that they can take an ordinary size suffix (their size suffix was formerly treated specially). This fixes one disassembly bug: 48C7C000000080 disassembles to mov rax,0x80000000, which reassembles to B800000080, which loads a different value. Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This commit is contained in:
Ben Rudiak-Gould
Cyrill Gorcunov
parent
57162eb084
commit
4e8396b5cf
6 changed files with 229 additions and 410 deletions
210
assemble.c
210
assemble.c
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@ -42,9 +42,8 @@
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* \7 - add 4 to both the primary and the secondary operand number
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* \10..\13 - a literal byte follows in the code stream, to be added
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* to the register value of operand 0..3
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* \14..\17 - a signed byte immediate operand, from operand 0..3
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* \20..\23 - a byte immediate operand, from operand 0..3
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* \24..\27 - an unsigned byte immediate operand, from operand 0..3
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* \24..\27 - a zero-extended byte immediate operand, from operand 0..3
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* \30..\33 - a word immediate operand, from operand 0..3
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* \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
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* assembly mode or the operand-size override on the operand
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@ -60,12 +59,6 @@
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* \74..\77 - a word constant, from the _segment_ part of operand 0..3
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* \1ab - a ModRM, calculated on EA in operand a, with the spare
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* field the register value of operand b.
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* \140..\143 - an immediate word or signed byte for operand 0..3
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* \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
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* is a signed byte rather than a word. Opcode byte follows.
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* \150..\153 - an immediate dword or signed byte for operand 0..3
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* \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
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* is a signed byte rather than a dword. Opcode byte follows.
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* \172\ab - the register number from operand a in bits 7..4, with
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* the 4-bit immediate from operand b in bits 3..0.
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* \173\xab - the register number from operand a in bits 7..4, with
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@ -74,9 +67,6 @@
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* an arbitrary value in bits 3..0 (assembled as zero.)
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* \2ab - a ModRM, calculated on EA in operand a, with the spare
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* field equal to digit b.
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* \250..\253 - same as \150..\153, except warn if the 64-bit operand
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* is not equal to the truncated and sign-extended 32-bit
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* operand; used for 32-bit immediates in 64-bit mode.
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* \254..\257 - a signed 32-bit operand to be extended to 64 bits.
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* \260..\263 - this instruction uses VEX/XOP rather than REX, with the
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* V field taken from operand 0..3.
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@ -100,8 +90,8 @@
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* \271 - instruction takes XRELEASE (F3) with or without lock
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* \272 - instruction takes XACQUIRE/XRELEASE with or without lock
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* \273 - instruction takes XACQUIRE/XRELEASE with lock only
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* \274..\277 - a signed byte immediate operand, from operand 0..3,
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* which is to be extended to the operand size.
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* \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
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* to the operand size (if o16/o32/o64 present) or the bit size
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* \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
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* \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
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* \312 - (disassembler only) invalid with non-default address size.
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@ -321,6 +311,17 @@ static void out(int64_t offset, int32_t segto, const void *data,
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outfmt->output(segto, data, type, size, segment, wrt);
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}
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static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
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{
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if (opx->segment != NO_SEG) {
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uint64_t data = opx->offset;
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out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
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} else {
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uint8_t byte = opx->offset;
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out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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}
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}
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static bool jmp_match(int32_t segment, int64_t offset, int bits,
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insn * ins, const struct itemplate *temp)
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{
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@ -765,36 +766,6 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
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}
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}
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static bool possible_sbyte(operand *o)
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{
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return o->wrt == NO_SEG && o->segment == NO_SEG &&
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!(o->opflags & OPFLAG_UNKNOWN) &&
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optimizing >= 0 && !(o->type & STRICT);
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}
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/* check that opn[op] is a signed byte of size 16 or 32 */
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static bool is_sbyte16(operand *o)
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{
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int16_t v;
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if (!possible_sbyte(o))
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return false;
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v = o->offset;
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return v >= -128 && v <= 127;
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}
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static bool is_sbyte32(operand *o)
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{
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int32_t v;
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if (!possible_sbyte(o))
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return false;
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v = o->offset;
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return v >= -128 && v <= 127;
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}
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static void bad_hle_warn(const insn * ins, uint8_t hleok)
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{
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enum prefixes rep_pfx = ins->prefixes[PPS_REP];
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@ -887,7 +858,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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codes++, length++;
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break;
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case4(014):
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case4(020):
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case4(024):
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length++;
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@ -939,24 +909,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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length += 2;
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break;
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case4(0140):
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length += is_sbyte16(opx) ? 1 : 2;
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break;
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case4(0144):
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codes++;
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length++;
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break;
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case4(0150):
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length += is_sbyte32(opx) ? 1 : 4;
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break;
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case4(0154):
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codes++;
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length++;
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break;
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case 0172:
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case 0173:
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codes++;
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@ -967,10 +919,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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length++;
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break;
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case4(0250):
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length += is_sbyte32(opx) ? 1 : 4;
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break;
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case4(0254):
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length += 4;
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break;
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@ -1320,45 +1268,12 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset += 1;
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break;
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case4(014):
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/*
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* The test for BITS8 and SBYTE here is intended to avoid
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* warning on optimizer actions due to SBYTE, while still
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* warn on explicit BYTE directives. Also warn, obviously,
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* if the optimizer isn't enabled.
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*/
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if (((opx->type & BITS8) ||
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!(opx->type & temp->opd[op1] & BYTENESS)) &&
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(opx->offset < -128 || opx->offset > 127)) {
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errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
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"signed byte value exceeds bounds");
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}
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if (opx->segment != NO_SEG) {
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data = opx->offset;
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out(offset, segment, &data, OUT_ADDRESS, 1,
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opx->segment, opx->wrt);
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} else {
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bytes[0] = opx->offset;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
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NO_SEG);
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}
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offset += 1;
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break;
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case4(020):
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if (opx->offset < -256 || opx->offset > 255) {
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errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
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"byte value exceeds bounds");
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}
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if (opx->segment != NO_SEG) {
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data = opx->offset;
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out(offset, segment, &data, OUT_ADDRESS, 1,
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opx->segment, opx->wrt);
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} else {
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bytes[0] = opx->offset;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
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NO_SEG);
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}
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out_imm8(offset, segment, opx);
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offset += 1;
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break;
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@ -1366,15 +1281,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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if (opx->offset < 0 || opx->offset > 255)
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errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
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"unsigned byte value exceeds bounds");
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if (opx->segment != NO_SEG) {
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data = opx->offset;
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out(offset, segment, &data, OUT_ADDRESS, 1,
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opx->segment, opx->wrt);
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} else {
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bytes[0] = opx->offset;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
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NO_SEG);
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}
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out_imm8(offset, segment, opx);
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offset += 1;
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break;
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@ -1495,54 +1402,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset += 2;
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break;
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case4(0140):
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data = opx->offset;
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warn_overflow_opd(opx, 2);
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if (is_sbyte16(opx)) {
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bytes[0] = data;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
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NO_SEG);
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offset++;
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} else {
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out(offset, segment, &data, OUT_ADDRESS, 2,
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opx->segment, opx->wrt);
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offset += 2;
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}
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break;
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case4(0144):
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EMIT_REX();
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bytes[0] = *codes++;
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if (is_sbyte16(opx))
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bytes[0] |= 2; /* s-bit */
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case4(0150):
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data = opx->offset;
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warn_overflow_opd(opx, 4);
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if (is_sbyte32(opx)) {
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bytes[0] = data;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
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NO_SEG);
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offset++;
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} else {
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out(offset, segment, &data, OUT_ADDRESS, 4,
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opx->segment, opx->wrt);
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offset += 4;
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}
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break;
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case4(0154):
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EMIT_REX();
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bytes[0] = *codes++;
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if (is_sbyte32(opx))
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bytes[0] |= 2; /* s-bit */
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0172:
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c = *codes++;
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opx = &ins->oprs[c >> 3];
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@ -1578,25 +1437,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset++;
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break;
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case4(0250):
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data = opx->offset;
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if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
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(int32_t)data != (int64_t)data) {
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errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
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"signed dword immediate exceeds bounds");
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}
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if (is_sbyte32(opx)) {
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bytes[0] = data;
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
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NO_SEG);
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offset++;
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} else {
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out(offset, segment, &data, OUT_ADDRESS, 4,
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opx->segment, opx->wrt);
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offset += 4;
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}
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break;
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case4(0254):
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data = opx->offset;
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if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
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@ -1652,8 +1492,15 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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if (uv > 127 && uv < (uint64_t)-128 &&
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(uv < um-128 || uv > um-1)) {
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/* If this wasn't explicitly byte-sized, warn as though we
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* had fallen through to the imm16/32/64 case.
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*/
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errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
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"signed byte value exceeds bounds");
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"%s value exceeds bounds",
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(opx->type & BITS8) ? "signed byte" :
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s == 16 ? "word" :
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s == 32 ? "dword" :
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"signed dword");
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}
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if (opx->segment != NO_SEG) {
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data = uv;
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@ -2197,10 +2044,11 @@ static enum match_result matches(const struct itemplate *itemp,
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if (type != instruction->oprs[j].type ||
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instruction->oprs[i].basereg != instruction->oprs[j].basereg)
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return MERR_INVALOP;
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} else if (itemp->opd[i] & ~type ||
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((itemp->opd[i] & SIZE_MASK) &&
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((itemp->opd[i] ^ type) & SIZE_MASK))) {
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if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
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} else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
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return MERR_INVALOP;
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} else if ((itemp->opd[i] & SIZE_MASK) &&
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(itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
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if (type & SIZE_MASK) {
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return MERR_INVALOP;
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} else if (!is_class(REGISTER, type)) {
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/*
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45
disasm.c
45
disasm.c
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@ -397,7 +397,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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int op1, op2;
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struct operand *opx, *opy;
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uint8_t opex = 0;
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int s_field_for = -1; /* No 144/154 series code encountered */
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bool vex_ok = false;
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int regmask = (segsize == 64) ? 15 : 7;
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enum ea_type eat = EA_SCALAR;
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@ -456,7 +455,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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break;
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}
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case4(014):
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case4(0274):
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opx->offset = (int8_t)*data++;
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opx->segment |= SEG_SIGNED;
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@ -488,11 +486,15 @@ static int matches(const struct itemplate *t, uint8_t *data,
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break;
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case4(040):
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case4(0254):
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opx->offset = getu32(data);
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data += 4;
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break;
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case4(0254):
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opx->offset = gets32(data);
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data += 4;
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break;
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case4(044):
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switch (asize) {
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case 16:
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@ -570,33 +572,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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break;
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}
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case4(0140):
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if (s_field_for == op1) {
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opx->offset = gets8(data);
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data++;
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} else {
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opx->offset = getu16(data);
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data += 2;
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}
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break;
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case4(0144):
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case4(0154):
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s_field_for = (*data & 0x02) ? op1 : -1;
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if ((*data++ & ~0x02) != *r++)
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return false;
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break;
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case4(0150):
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if (s_field_for == op1) {
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opx->offset = gets8(data);
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data++;
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} else {
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opx->offset = getu32(data);
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data += 4;
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}
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break;
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case 0172:
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{
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uint8_t ximm = *data++;
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@ -647,16 +622,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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break;
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}
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case4(0250):
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if (s_field_for == op1) {
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opx->offset = gets8(data);
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data++;
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} else {
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opx->offset = gets32(data);
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data += 4;
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}
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break;
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case4(0260):
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case 0270:
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{
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|
|
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301
insns.dat
301
insns.dat
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@ -86,23 +86,28 @@ ADC reg32,mem [rm: o32 13 /r] 386,SM
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ADC reg32,reg32 [rm: o32 13 /r] 386
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ADC reg64,mem [rm: o64 13 /r] X64,SM
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ADC reg64,reg64 [rm: o64 13 /r] X64
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ADC rm16,imm8 [mi: hle o16 83 /2 ibx] 8086,LOCK
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ADC rm32,imm8 [mi: hle o32 83 /2 ibx] 386,LOCK
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ADC rm64,imm8 [mi: hle o64 83 /2 ibx] X64,LOCK
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ADC rm16,imm8 [mi: hle o16 83 /2 ib,s] 8086,LOCK
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ADC rm32,imm8 [mi: hle o32 83 /2 ib,s] 386,LOCK
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ADC rm64,imm8 [mi: hle o64 83 /2 ib,s] X64,LOCK
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ADC reg_al,imm [-i: 14 ib] 8086,SM
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ADC reg_ax,sbyte16 [mi: o16 83 /2 ibx] 8086,SM
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ADC reg_ax,sbyteword [mi: o16 83 /2 ib,s] 8086,SM,ND
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ADC reg_ax,imm [-i: o16 15 iw] 8086,SM
|
||||
ADC reg_eax,sbyte32 [mi: o32 83 /2 ibx] 386,SM
|
||||
ADC reg_eax,sbytedword [mi: o32 83 /2 ib,s] 386,SM,ND
|
||||
ADC reg_eax,imm [-i: o32 15 id] 386,SM
|
||||
ADC reg_rax,sbyte64 [mi: o64 83 /2 ibx] X64,SM
|
||||
ADC reg_rax,imm [-i: o64 15 idx] X64,SM
|
||||
ADC reg_rax,sbytedword [mi: o64 83 /2 ib,s] X64,SM,ND
|
||||
ADC reg_rax,imm [-i: o64 15 id,s] X64,SM
|
||||
ADC rm8,imm [mi: hle 80 /2 ib] 8086,SM,LOCK
|
||||
ADC rm16,imm [mi: hle o16 81+s /2 ibw] 8086,SM,LOCK
|
||||
ADC rm32,imm [mi: hle o32 81+s /2 ibd] 386,SM,LOCK
|
||||
ADC rm64,imm [mi: hle o64 81+s /2 ibd,s] X64,SM,LOCK
|
||||
ADC mem,imm8 [mi: hle 80 /2 ib] 8086,SM,LOCK
|
||||
ADC mem,imm16 [mi: hle o16 81+s /2 ibw] 8086,SM,LOCK
|
||||
ADC mem,imm32 [mi: hle o32 81+s /2 ibd] 386,SM,LOCK
|
||||
ADC rm16,sbyteword [mi: hle o16 83 /2 ib,s] 8086,SM,LOCK,ND
|
||||
ADC rm16,imm [mi: hle o16 81 /2 iw] 8086,SM,LOCK
|
||||
ADC rm32,sbytedword [mi: hle o32 83 /2 ib,s] 386,SM,LOCK,ND
|
||||
ADC rm32,imm [mi: hle o32 81 /2 id] 386,SM,LOCK
|
||||
ADC rm64,sbytedword [mi: hle o64 83 /2 ib,s] X64,SM,LOCK,ND
|
||||
ADC rm64,imm [mi: hle o64 81 /2 id,s] X64,SM,LOCK
|
||||
ADC mem,imm8 [mi: hle 80 /2 ib] 8086,SM,LOCK,ND
|
||||
ADC mem,sbyteword16 [mi: hle o16 83 /2 ib,s] 8086,SM,LOCK,ND
|
||||
ADC mem,imm16 [mi: hle o16 81 /2 iw] 8086,SM,LOCK
|
||||
ADC mem,sbytedword32 [mi: hle o32 83 /2 ib,s] 386,SM,LOCK,ND
|
||||
ADC mem,imm32 [mi: hle o32 81 /2 id] 386,SM,LOCK
|
||||
ADC rm8,imm [mi: hle 82 /2 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
ADD mem,reg8 [mr: hle 00 /r] 8086,SM,LOCK
|
||||
ADD reg8,reg8 [mr: 00 /r] 8086
|
||||
|
|
@ -120,23 +125,28 @@ ADD reg32,mem [rm: o32 03 /r] 386,SM
|
|||
ADD reg32,reg32 [rm: o32 03 /r] 386
|
||||
ADD reg64,mem [rm: o64 03 /r] X64,SM
|
||||
ADD reg64,reg64 [rm: o64 03 /r] X64
|
||||
ADD rm16,imm8 [mi: hle o16 83 /0 ibx] 8086,LOCK
|
||||
ADD rm32,imm8 [mi: hle o32 83 /0 ibx] 386,LOCK
|
||||
ADD rm64,imm8 [mi: hle o64 83 /0 ibx] X64,LOCK
|
||||
ADD rm16,imm8 [mi: hle o16 83 /0 ib,s] 8086,LOCK
|
||||
ADD rm32,imm8 [mi: hle o32 83 /0 ib,s] 386,LOCK
|
||||
ADD rm64,imm8 [mi: hle o64 83 /0 ib,s] X64,LOCK
|
||||
ADD reg_al,imm [-i: 04 ib] 8086,SM
|
||||
ADD reg_ax,sbyte16 [mi: o16 83 /0 ibx] 8086,SM
|
||||
ADD reg_ax,sbyteword [mi: o16 83 /0 ib,s] 8086,SM,ND
|
||||
ADD reg_ax,imm [-i: o16 05 iw] 8086,SM
|
||||
ADD reg_eax,sbyte32 [mi: o32 83 /0 ibx] 386,SM
|
||||
ADD reg_eax,sbytedword [mi: o32 83 /0 ib,s] 386,SM,ND
|
||||
ADD reg_eax,imm [-i: o32 05 id] 386,SM
|
||||
ADD reg_rax,sbyte64 [mi: o64 83 /0 ibx] X64,SM
|
||||
ADD reg_rax,imm [-i: o64 05 idx] X64,SM
|
||||
ADD reg_rax,sbytedword [mi: o64 83 /0 ib,s] X64,SM,ND
|
||||
ADD reg_rax,imm [-i: o64 05 id,s] X64,SM
|
||||
ADD rm8,imm [mi: hle 80 /0 ib] 8086,SM,LOCK
|
||||
ADD rm16,imm [mi: hle o16 81+s /0 ibw] 8086,SM,LOCK
|
||||
ADD rm32,imm [mi: hle o32 81+s /0 ibd] 386,SM,LOCK
|
||||
ADD rm64,imm [mi: hle o64 81+s /0 ibd,s] X64,SM,LOCK
|
||||
ADD rm16,sbyteword [mi: hle o16 83 /0 ib,s] 8086,SM,LOCK,ND
|
||||
ADD rm16,imm [mi: hle o16 81 /0 iw] 8086,SM,LOCK
|
||||
ADD rm32,sbytedword [mi: hle o32 83 /0 ib,s] 386,SM,LOCK,ND
|
||||
ADD rm32,imm [mi: hle o32 81 /0 id] 386,SM,LOCK
|
||||
ADD rm64,sbytedword [mi: hle o64 83 /0 ib,s] X64,SM,LOCK,ND
|
||||
ADD rm64,imm [mi: hle o64 81 /0 id,s] X64,SM,LOCK
|
||||
ADD mem,imm8 [mi: hle 80 /0 ib] 8086,SM,LOCK
|
||||
ADD mem,imm16 [mi: hle o16 81+s /0 ibw] 8086,SM,LOCK
|
||||
ADD mem,imm32 [mi: hle o32 81+s /0 ibd] 386,SM,LOCK
|
||||
ADD mem,sbyteword16 [mi: hle o16 83 /0 ib,s] 8086,SM,LOCK,ND
|
||||
ADD mem,imm16 [mi: hle o16 81 /0 iw] 8086,SM,LOCK
|
||||
ADD mem,sbytedword32 [mi: hle o32 83 /0 ib,s] 386,SM,LOCK,ND
|
||||
ADD mem,imm32 [mi: hle o32 81 /0 id] 386,SM,LOCK
|
||||
ADD rm8,imm [mi: hle 82 /0 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
AND mem,reg8 [mr: hle 20 /r] 8086,SM,LOCK
|
||||
AND reg8,reg8 [mr: 20 /r] 8086
|
||||
|
|
@ -154,23 +164,28 @@ AND reg32,mem [rm: o32 23 /r] 386,SM
|
|||
AND reg32,reg32 [rm: o32 23 /r] 386
|
||||
AND reg64,mem [rm: o64 23 /r] X64,SM
|
||||
AND reg64,reg64 [rm: o64 23 /r] X64
|
||||
AND rm16,imm8 [mi: hle o16 83 /4 ibx] 8086,LOCK
|
||||
AND rm32,imm8 [mi: hle o32 83 /4 ibx] 386,LOCK
|
||||
AND rm64,imm8 [mi: hle o64 83 /4 ibx] X64,LOCK
|
||||
AND rm16,imm8 [mi: hle o16 83 /4 ib,s] 8086,LOCK
|
||||
AND rm32,imm8 [mi: hle o32 83 /4 ib,s] 386,LOCK
|
||||
AND rm64,imm8 [mi: hle o64 83 /4 ib,s] X64,LOCK
|
||||
AND reg_al,imm [-i: 24 ib] 8086,SM
|
||||
AND reg_ax,sbyte16 [mi: o16 83 /4 ibx] 8086,SM
|
||||
AND reg_ax,sbyteword [mi: o16 83 /4 ib,s] 8086,SM,ND
|
||||
AND reg_ax,imm [-i: o16 25 iw] 8086,SM
|
||||
AND reg_eax,sbyte32 [mi: o32 83 /4 ibx] 386,SM
|
||||
AND reg_eax,sbytedword [mi: o32 83 /4 ib,s] 386,SM,ND
|
||||
AND reg_eax,imm [-i: o32 25 id] 386,SM
|
||||
AND reg_rax,sbyte64 [mi: o64 83 /4 ibx] X64,SM
|
||||
AND reg_rax,imm [-i: o64 25 idx] X64,SM
|
||||
AND reg_rax,sbytedword [mi: o64 83 /4 ib,s] X64,SM,ND
|
||||
AND reg_rax,imm [-i: o64 25 id,s] X64,SM
|
||||
AND rm8,imm [mi: hle 80 /4 ib] 8086,SM,LOCK
|
||||
AND rm16,imm [mi: hle o16 81+s /4 ibw] 8086,SM,LOCK
|
||||
AND rm32,imm [mi: hle o32 81+s /4 ibd] 386,SM,LOCK
|
||||
AND rm64,imm [mi: hle o64 81+s /4 ibd,s] X64,SM,LOCK
|
||||
AND rm16,sbyteword [mi: hle o16 83 /4 ib,s] 8086,SM,LOCK,ND
|
||||
AND rm16,imm [mi: hle o16 81 /4 iw] 8086,SM,LOCK
|
||||
AND rm32,sbytedword [mi: hle o32 83 /4 ib,s] 386,SM,LOCK,ND
|
||||
AND rm32,imm [mi: hle o32 81 /4 id] 386,SM,LOCK
|
||||
AND rm64,sbytedword [mi: hle o64 83 /4 ib,s] X64,SM,LOCK,ND
|
||||
AND rm64,imm [mi: hle o64 81 /4 id,s] X64,SM,LOCK
|
||||
AND mem,imm8 [mi: hle 80 /4 ib] 8086,SM,LOCK
|
||||
AND mem,imm16 [mi: hle o16 81+s /4 ibw] 8086,SM,LOCK
|
||||
AND mem,imm32 [mi: hle o32 81+s /4 ibd] 386,SM,LOCK
|
||||
AND mem,sbyteword16 [mi: hle o16 83 /4 ib,s] 8086,SM,LOCK,ND
|
||||
AND mem,imm16 [mi: hle o16 81 /4 iw] 8086,SM,LOCK
|
||||
AND mem,sbytedword32 [mi: hle o32 83 /4 ib,s] 386,SM,LOCK,ND
|
||||
AND mem,imm32 [mi: hle o32 81 /4 id] 386,SM,LOCK
|
||||
AND rm8,imm [mi: hle 82 /4 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
ARPL mem,reg16 [mr: 63 /r] 286,PROT,SM,NOLONG
|
||||
ARPL reg16,reg16 [mr: 63 /r] 286,PROT,NOLONG
|
||||
|
|
@ -282,23 +297,28 @@ CMP reg32,mem [rm: o32 3b /r] 386,SM
|
|||
CMP reg32,reg32 [rm: o32 3b /r] 386
|
||||
CMP reg64,mem [rm: o64 3b /r] X64,SM
|
||||
CMP reg64,reg64 [rm: o64 3b /r] X64
|
||||
CMP rm16,imm8 [mi: o16 83 /7 ibx] 8086
|
||||
CMP rm32,imm8 [mi: o32 83 /7 ibx] 386
|
||||
CMP rm64,imm8 [mi: o64 83 /7 ibx] X64
|
||||
CMP rm16,imm8 [mi: o16 83 /7 ib,s] 8086
|
||||
CMP rm32,imm8 [mi: o32 83 /7 ib,s] 386
|
||||
CMP rm64,imm8 [mi: o64 83 /7 ib,s] X64
|
||||
CMP reg_al,imm [-i: 3c ib] 8086,SM
|
||||
CMP reg_ax,sbyte16 [mi: o16 83 /7 ibx] 8086,SM
|
||||
CMP reg_ax,sbyteword [mi: o16 83 /7 ib,s] 8086,SM,ND
|
||||
CMP reg_ax,imm [-i: o16 3d iw] 8086,SM
|
||||
CMP reg_eax,sbyte32 [mi: o32 83 /7 ibx] 386,SM
|
||||
CMP reg_eax,sbytedword [mi: o32 83 /7 ib,s] 386,SM,ND
|
||||
CMP reg_eax,imm [-i: o32 3d id] 386,SM
|
||||
CMP reg_rax,sbyte64 [mi: o64 83 /7 ibx] X64,SM
|
||||
CMP reg_rax,imm [-i: o64 3d idx] X64,SM
|
||||
CMP reg_rax,sbytedword [mi: o64 83 /7 ib,s] X64,SM,ND
|
||||
CMP reg_rax,imm [-i: o64 3d id,s] X64,SM
|
||||
CMP rm8,imm [mi: 80 /7 ib] 8086,SM
|
||||
CMP rm16,imm [mi: o16 81+s /7 ibw] 8086,SM
|
||||
CMP rm32,imm [mi: o32 81+s /7 ibd] 386,SM
|
||||
CMP rm64,imm [mi: o64 81+s /7 ibd,s] X64,SM
|
||||
CMP rm16,sbyteword [mi: o16 83 /7 ib,s] 8086,SM,ND
|
||||
CMP rm16,imm [mi: o16 81 /7 iw] 8086,SM
|
||||
CMP rm32,sbytedword [mi: o32 83 /7 ib,s] 386,SM,ND
|
||||
CMP rm32,imm [mi: o32 81 /7 id] 386,SM
|
||||
CMP rm64,sbytedword [mi: o64 83 /7 ib,s] X64,SM,ND
|
||||
CMP rm64,imm [mi: o64 81 /7 id,s] X64,SM
|
||||
CMP mem,imm8 [mi: 80 /7 ib] 8086,SM
|
||||
CMP mem,imm16 [mi: o16 81+s /7 ibw] 8086,SM
|
||||
CMP mem,imm32 [mi: o32 81+s /7 ibd] 386,SM
|
||||
CMP mem,sbyteword16 [mi: o16 83 /7 ib,s] 8086,SM,ND
|
||||
CMP mem,imm16 [mi: o16 81 /7 iw] 8086,SM
|
||||
CMP mem,sbytedword32 [mi: o32 83 /7 ib,s] 386,SM,ND
|
||||
CMP mem,imm32 [mi: o32 81 /7 id] 386,SM
|
||||
CMP rm8,imm [mi: 82 /7 ib] 8086,SM,ND,NOLONG
|
||||
CMPSB void [ repe a6] 8086
|
||||
CMPSD void [ repe o32 a7] 386
|
||||
|
|
@ -582,41 +602,41 @@ IMUL reg32,reg32 [rm: o32 0f af /r] 386
|
|||
IMUL reg64,mem [rm: o64 0f af /r] X64,SM
|
||||
IMUL reg64,reg64 [rm: o64 0f af /r] X64
|
||||
IMUL reg16,mem,imm8 [rmi: o16 6b /r ib,s] 186,SM
|
||||
IMUL reg16,mem,sbyte16 [rmi: o16 6b /r ib,s] 186,SM,ND
|
||||
IMUL reg16,mem,sbyteword [rmi: o16 6b /r ib,s] 186,SM,ND
|
||||
IMUL reg16,mem,imm16 [rmi: o16 69 /r iw] 186,SM
|
||||
IMUL reg16,mem,imm [rmi: o16 69+s /r ibw] 186,SM,ND
|
||||
IMUL reg16,mem,imm [rmi: o16 69 /r iw] 186,SM,ND
|
||||
IMUL reg16,reg16,imm8 [rmi: o16 6b /r ib,s] 186
|
||||
IMUL reg16,reg16,sbyte16 [rmi: o16 6b /r ib,s] 186,SM,ND
|
||||
IMUL reg16,reg16,sbyteword [rmi: o16 6b /r ib,s] 186,SM,ND
|
||||
IMUL reg16,reg16,imm16 [rmi: o16 69 /r iw] 186
|
||||
IMUL reg16,reg16,imm [rmi: o16 69+s /r ibw] 186,SM,ND
|
||||
IMUL reg16,reg16,imm [rmi: o16 69 /r iw] 186,SM,ND
|
||||
IMUL reg32,mem,imm8 [rmi: o32 6b /r ib,s] 386,SM
|
||||
IMUL reg32,mem,sbyte32 [rmi: o32 6b /r ib,s] 386,SM,ND
|
||||
IMUL reg32,mem,sbytedword [rmi: o32 6b /r ib,s] 386,SM,ND
|
||||
IMUL reg32,mem,imm32 [rmi: o32 69 /r id] 386,SM
|
||||
IMUL reg32,mem,imm [rmi: o32 69+s /r ibd] 386,SM,ND
|
||||
IMUL reg32,mem,imm [rmi: o32 69 /r id] 386,SM,ND
|
||||
IMUL reg32,reg32,imm8 [rmi: o32 6b /r ib,s] 386
|
||||
IMUL reg32,reg32,sbyte32 [rmi: o32 6b /r ib,s] 386,SM,ND
|
||||
IMUL reg32,reg32,sbytedword [rmi: o32 6b /r ib,s] 386,SM,ND
|
||||
IMUL reg32,reg32,imm32 [rmi: o32 69 /r id] 386
|
||||
IMUL reg32,reg32,imm [rmi: o32 69+s /r ibd] 386,SM,ND
|
||||
IMUL reg32,reg32,imm [rmi: o32 69 /r id] 386,SM,ND
|
||||
IMUL reg64,mem,imm8 [rmi: o64 6b /r ib,s] X64,SM
|
||||
IMUL reg64,mem,sbyte64 [rmi: o64 6b /r ib,s] X64,SM,ND
|
||||
IMUL reg64,mem,sbytedword [rmi: o64 6b /r ib,s] X64,SM,ND
|
||||
IMUL reg64,mem,imm32 [rmi: o64 69 /r id] X64,SM
|
||||
IMUL reg64,mem,imm [rmi: o64 69+s /r ibd,s] X64,SM,ND
|
||||
IMUL reg64,mem,imm [rmi: o64 69 /r id,s] X64,SM,ND
|
||||
IMUL reg64,reg64,imm8 [rmi: o64 6b /r ib,s] X64
|
||||
IMUL reg64,reg64,sbyte64 [rmi: o64 6b /r ib,s] X64,SM,ND
|
||||
IMUL reg64,reg64,sbytedword [rmi: o64 6b /r ib,s] X64,SM,ND
|
||||
IMUL reg64,reg64,imm32 [rmi: o64 69 /r id] X64
|
||||
IMUL reg64,reg64,imm [rmi: o64 69+s /r ibd,s] X64,SM,ND
|
||||
IMUL reg64,reg64,imm [rmi: o64 69 /r id,s] X64,SM,ND
|
||||
IMUL reg16,imm8 [r+mi: o16 6b /r ib,s] 186
|
||||
IMUL reg16,sbyte16 [r+mi: o16 6b /r ib,s] 186,SM,ND
|
||||
IMUL reg16,sbyteword [r+mi: o16 6b /r ib,s] 186,SM,ND
|
||||
IMUL reg16,imm16 [r+mi: o16 69 /r iw] 186
|
||||
IMUL reg16,imm [r+mi: o16 69+s /r ibw] 186,SM,ND
|
||||
IMUL reg16,imm [r+mi: o16 69 /r iw] 186,SM,ND
|
||||
IMUL reg32,imm8 [r+mi: o32 6b /r ib,s] 386
|
||||
IMUL reg32,sbyte32 [r+mi: o32 6b /r ib,s] 386,SM,ND
|
||||
IMUL reg32,sbytedword [r+mi: o32 6b /r ib,s] 386,SM,ND
|
||||
IMUL reg32,imm32 [r+mi: o32 69 /r id] 386
|
||||
IMUL reg32,imm [r+mi: o32 69+s /r ibd] 386,SM,ND
|
||||
IMUL reg32,imm [r+mi: o32 69 /r id] 386,SM,ND
|
||||
IMUL reg64,imm8 [r+mi: o64 6b /r ib,s] X64
|
||||
IMUL reg64,sbyte64 [r+mi: o64 6b /r ib,s] X64,SM,ND
|
||||
IMUL reg64,imm32 [r+mi: o64 69 /r idx] X64
|
||||
IMUL reg64,imm [r+mi: o64 69+s /r ibd,s] X64,SM,ND
|
||||
IMUL reg64,sbytedword [r+mi: o64 6b /r ib,s] X64,SM,ND
|
||||
IMUL reg64,imm32 [r+mi: o64 69 /r id,s] X64
|
||||
IMUL reg64,imm [r+mi: o64 69 /r id,s] X64,SM,ND
|
||||
IN reg_al,imm [-i: e4 ib,u] 8086,SB
|
||||
IN reg_ax,imm [-i: o16 e5 ib,u] 8086,SB
|
||||
IN reg_eax,imm [-i: o32 e5 ib,u] 386,SB
|
||||
|
|
@ -824,14 +844,14 @@ MOV reg64,reg64 [rm: o64 8b /r] X64
|
|||
MOV reg8,imm [ri: b0+r ib] 8086,SM
|
||||
MOV reg16,imm [ri: o16 b8+r iw] 8086,SM
|
||||
MOV reg32,imm [ri: o32 b8+r id] 386,SM
|
||||
MOV reg64,udword64 [ri: o64nw b8+r id] X64,SM,OPT,ND
|
||||
MOV reg64,sdword64 [mi: o64 c7 /0 idx] X64,SM,OPT,ND
|
||||
MOV reg64,udword [ri: o64nw b8+r id] X64,SM,OPT,ND
|
||||
MOV reg64,sdword [mi: o64 c7 /0 id,s] X64,SM,OPT,ND
|
||||
MOV reg64,imm [ri: o64 b8+r iq] X64,SM
|
||||
MOV rm8,imm [mi: hlexr c6 /0 ib] 8086,SM
|
||||
MOV rm16,imm [mi: hlexr o16 c7 /0 iw] 8086,SM
|
||||
MOV rm32,imm [mi: hlexr o32 c7 /0 id] 386,SM
|
||||
MOV rm64,imm [mi: hlexr o64 c7 /0 idx] X64,SM
|
||||
MOV rm64,imm32 [mi: hlexr o64 c7 /0 idx] X64
|
||||
MOV rm64,imm [mi: hlexr o64 c7 /0 id,s] X64,SM
|
||||
MOV rm64,imm32 [mi: hlexr o64 c7 /0 id,s] X64
|
||||
MOV mem,imm8 [mi: hlexr c6 /0 ib] 8086,SM
|
||||
MOV mem,imm16 [mi: hlexr o16 c7 /0 iw] 8086,SM
|
||||
MOV mem,imm32 [mi: hlexr o32 c7 /0 id] 386,SM
|
||||
|
|
@ -895,23 +915,28 @@ OR reg32,mem [rm: o32 0b /r] 386,SM
|
|||
OR reg32,reg32 [rm: o32 0b /r] 386
|
||||
OR reg64,mem [rm: o64 0b /r] X64,SM
|
||||
OR reg64,reg64 [rm: o64 0b /r] X64
|
||||
OR rm16,imm8 [mi: hle o16 83 /1 ibx] 8086,LOCK
|
||||
OR rm32,imm8 [mi: hle o32 83 /1 ibx] 386,LOCK
|
||||
OR rm64,imm8 [mi: hle o64 83 /1 ibx] X64,LOCK
|
||||
OR rm16,imm8 [mi: hle o16 83 /1 ib,s] 8086,LOCK
|
||||
OR rm32,imm8 [mi: hle o32 83 /1 ib,s] 386,LOCK
|
||||
OR rm64,imm8 [mi: hle o64 83 /1 ib,s] X64,LOCK
|
||||
OR reg_al,imm [-i: 0c ib] 8086,SM
|
||||
OR reg_ax,sbyte16 [mi: o16 83 /1 ibx] 8086,SM
|
||||
OR reg_ax,sbyteword [mi: o16 83 /1 ib,s] 8086,SM,ND
|
||||
OR reg_ax,imm [-i: o16 0d iw] 8086,SM
|
||||
OR reg_eax,sbyte32 [mi: o32 83 /1 ibx] 386,SM
|
||||
OR reg_eax,sbytedword [mi: o32 83 /1 ib,s] 386,SM,ND
|
||||
OR reg_eax,imm [-i: o32 0d id] 386,SM
|
||||
OR reg_rax,sbyte64 [mi: o64 83 /1 ibx] X64,SM
|
||||
OR reg_rax,imm [-i: o64 0d idx] X64,SM
|
||||
OR reg_rax,sbytedword [mi: o64 83 /1 ib,s] X64,SM,ND
|
||||
OR reg_rax,imm [-i: o64 0d id,s] X64,SM
|
||||
OR rm8,imm [mi: hle 80 /1 ib] 8086,SM,LOCK
|
||||
OR rm16,imm [mi: hle o16 81+s /1 ibw] 8086,SM,LOCK
|
||||
OR rm32,imm [mi: hle o32 81+s /1 ibd] 386,SM,LOCK
|
||||
OR rm64,imm [mi: hle o64 81+s /1 ibd,s] X64,SM,LOCK
|
||||
OR rm16,sbyteword [mi: hle o16 83 /1 ib,s] 8086,SM,LOCK,ND
|
||||
OR rm16,imm [mi: hle o16 81 /1 iw] 8086,SM,LOCK
|
||||
OR rm32,sbytedword [mi: hle o32 83 /1 ib,s] 386,SM,LOCK,ND
|
||||
OR rm32,imm [mi: hle o32 81 /1 id] 386,SM,LOCK
|
||||
OR rm64,sbytedword [mi: hle o64 83 /1 ib,s] X64,SM,LOCK,ND
|
||||
OR rm64,imm [mi: hle o64 81 /1 id,s] X64,SM,LOCK
|
||||
OR mem,imm8 [mi: hle 80 /1 ib] 8086,SM,LOCK
|
||||
OR mem,imm16 [mi: hle o16 81+s /1 ibw] 8086,SM,LOCK
|
||||
OR mem,imm32 [mi: hle o32 81+s /1 ibd] 386,SM,LOCK
|
||||
OR mem,sbyteword16 [mi: hle o16 83 /1 ib,s] 8086,SM,LOCK,ND
|
||||
OR mem,imm16 [mi: hle o16 81 /1 iw] 8086,SM,LOCK
|
||||
OR mem,sbytedword32 [mi: hle o32 83 /1 ib,s] 386,SM,LOCK,ND
|
||||
OR mem,imm32 [mi: hle o32 81 /1 id] 386,SM,LOCK
|
||||
OR rm8,imm [mi: hle 82 /1 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
OUT imm,reg_al [i-: e6 ib,u] 8086,SB
|
||||
OUT imm,reg_ax [i-: o16 e7 ib,u] 8086,SB
|
||||
|
|
@ -1032,12 +1057,17 @@ PUSH rm64 [m: o64nw ff /6] X64
|
|||
PUSH reg_cs [-: pushseg] 8086,NOLONG
|
||||
PUSH reg_dess [-: pushseg] 8086,NOLONG
|
||||
PUSH reg_fsgs [-: 0f pushseg2] 386
|
||||
PUSH imm8 [i: 6a ibx] 186
|
||||
PUSH imm16 [i: o16 68+s ibw] 186,AR0,SZ
|
||||
PUSH imm32 [i: o32 68+s ibd] 386,NOLONG,AR0,SZ
|
||||
PUSH imm32 [i: o32 68+s ibd] 386,NOLONG,SD
|
||||
PUSH imm32 [i: o64nw 68+s ibd,s] X64,AR0,SZ
|
||||
PUSH imm64 [i: o64nw 68+s ibd,s] X64,AR0,SZ
|
||||
PUSH imm8 [i: 6a ib,s] 186
|
||||
PUSH sbyteword16 [i: o16 6a ib,s] 186,AR0,SZ,ND
|
||||
PUSH imm16 [i: o16 68 iw] 186,AR0,SZ
|
||||
PUSH sbytedword32 [i: o32 6a ib,s] 386,NOLONG,AR0,SZ,ND
|
||||
PUSH imm32 [i: o32 68 id] 386,NOLONG,AR0,SZ
|
||||
PUSH sbytedword32 [i: o32 6a ib,s] 386,NOLONG,SD,ND
|
||||
PUSH imm32 [i: o32 68 id] 386,NOLONG,SD
|
||||
PUSH sbytedword64 [i: o64nw 6a ib,s] X64,AR0,SZ,ND
|
||||
PUSH imm64 [i: o64nw 68 id,s] X64,AR0,SZ
|
||||
PUSH sbytedword32 [i: o64nw 6a ib,s] X64,AR0,SZ,ND
|
||||
PUSH imm32 [i: o64nw 68 id,s] X64,AR0,SZ
|
||||
PUSHA void [ odf 60] 186,NOLONG
|
||||
PUSHAD void [ o32 60] 386,NOLONG
|
||||
PUSHAW void [ o16 60] 186,NOLONG
|
||||
|
|
@ -1152,23 +1182,28 @@ SBB reg32,mem [rm: o32 1b /r] 386,SM
|
|||
SBB reg32,reg32 [rm: o32 1b /r] 386
|
||||
SBB reg64,mem [rm: o64 1b /r] X64,SM
|
||||
SBB reg64,reg64 [rm: o64 1b /r] X64
|
||||
SBB rm16,imm8 [mi: hle o16 83 /3 ibx] 8086,LOCK
|
||||
SBB rm32,imm8 [mi: hle o32 83 /3 ibx] 386,LOCK
|
||||
SBB rm64,imm8 [mi: hle o64 83 /3 ibx] X64,LOCK
|
||||
SBB rm16,imm8 [mi: hle o16 83 /3 ib,s] 8086,LOCK
|
||||
SBB rm32,imm8 [mi: hle o32 83 /3 ib,s] 386,LOCK
|
||||
SBB rm64,imm8 [mi: hle o64 83 /3 ib,s] X64,LOCK
|
||||
SBB reg_al,imm [-i: 1c ib] 8086,SM
|
||||
SBB reg_ax,sbyte16 [mi: o16 83 /3 ibx] 8086,SM
|
||||
SBB reg_ax,sbyteword [mi: o16 83 /3 ib,s] 8086,SM,ND
|
||||
SBB reg_ax,imm [-i: o16 1d iw] 8086,SM
|
||||
SBB reg_eax,sbyte32 [mi: o32 83 /3 ibx] 386,SM
|
||||
SBB reg_eax,sbytedword [mi: o32 83 /3 ib,s] 386,SM,ND
|
||||
SBB reg_eax,imm [-i: o32 1d id] 386,SM
|
||||
SBB reg_rax,sbyte64 [mi: o64 83 /3 ibx] X64,SM
|
||||
SBB reg_rax,imm [-i: o64 1d idx] X64,SM
|
||||
SBB reg_rax,sbytedword [mi: o64 83 /3 ib,s] X64,SM,ND
|
||||
SBB reg_rax,imm [-i: o64 1d id,s] X64,SM
|
||||
SBB rm8,imm [mi: hle 80 /3 ib] 8086,SM,LOCK
|
||||
SBB rm16,imm [mi: hle o16 81+s /3 ibw] 8086,SM,LOCK
|
||||
SBB rm32,imm [mi: hle o32 81+s /3 ibd] 386,SM,LOCK
|
||||
SBB rm64,imm [mi: hle o64 81+s /3 ibd,s] X64,SM,LOCK
|
||||
SBB rm16,sbyteword [mi: hle o16 83 /3 ib,s] 8086,SM,LOCK,ND
|
||||
SBB rm16,imm [mi: hle o16 81 /3 iw] 8086,SM,LOCK
|
||||
SBB rm32,sbytedword [mi: hle o32 83 /3 ib,s] 386,SM,LOCK,ND
|
||||
SBB rm32,imm [mi: hle o32 81 /3 id] 386,SM,LOCK
|
||||
SBB rm64,sbytedword [mi: hle o64 83 /3 ib,s] X64,SM,LOCK,ND
|
||||
SBB rm64,imm [mi: hle o64 81 /3 id,s] X64,SM,LOCK
|
||||
SBB mem,imm8 [mi: hle 80 /3 ib] 8086,SM,LOCK
|
||||
SBB mem,imm16 [mi: hle o16 81+s /3 ibw] 8086,SM,LOCK
|
||||
SBB mem,imm32 [mi: hle o32 81+s /3 ibd] 386,SM,LOCK
|
||||
SBB mem,sbyteword16 [mi: hle o16 83 /3 ib,s] 8086,SM,LOCK,ND
|
||||
SBB mem,imm16 [mi: hle o16 81 /3 iw] 8086,SM,LOCK
|
||||
SBB mem,sbytedword32 [mi: hle o32 83 /3 ib,s] 386,SM,LOCK,ND
|
||||
SBB mem,imm32 [mi: hle o32 81 /3 id] 386,SM,LOCK
|
||||
SBB rm8,imm [mi: hle 82 /3 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
SCASB void [ repe ae] 8086
|
||||
SCASD void [ repe o32 af] 386
|
||||
|
|
@ -1268,23 +1303,28 @@ SUB reg32,mem [rm: o32 2b /r] 386,SM
|
|||
SUB reg32,reg32 [rm: o32 2b /r] 386
|
||||
SUB reg64,mem [rm: o64 2b /r] X64,SM
|
||||
SUB reg64,reg64 [rm: o64 2b /r] X64
|
||||
SUB rm16,imm8 [mi: hle o16 83 /5 ibx] 8086,LOCK
|
||||
SUB rm32,imm8 [mi: hle o32 83 /5 ibx] 386,LOCK
|
||||
SUB rm64,imm8 [mi: hle o64 83 /5 ibx] X64,LOCK
|
||||
SUB rm16,imm8 [mi: hle o16 83 /5 ib,s] 8086,LOCK
|
||||
SUB rm32,imm8 [mi: hle o32 83 /5 ib,s] 386,LOCK
|
||||
SUB rm64,imm8 [mi: hle o64 83 /5 ib,s] X64,LOCK
|
||||
SUB reg_al,imm [-i: 2c ib] 8086,SM
|
||||
SUB reg_ax,sbyte16 [mi: o16 83 /5 ibx] 8086,SM
|
||||
SUB reg_ax,sbyteword [mi: o16 83 /5 ib,s] 8086,SM,ND
|
||||
SUB reg_ax,imm [-i: o16 2d iw] 8086,SM
|
||||
SUB reg_eax,sbyte32 [mi: o32 83 /5 ibx] 386,SM
|
||||
SUB reg_eax,sbytedword [mi: o32 83 /5 ib,s] 386,SM,ND
|
||||
SUB reg_eax,imm [-i: o32 2d id] 386,SM
|
||||
SUB reg_rax,sbyte64 [mi: o64 83 /5 ibx] X64,SM
|
||||
SUB reg_rax,imm [-i: o64 2d idx] X64,SM
|
||||
SUB reg_rax,sbytedword [mi: o64 83 /5 ib,s] X64,SM,ND
|
||||
SUB reg_rax,imm [-i: o64 2d id,s] X64,SM
|
||||
SUB rm8,imm [mi: hle 80 /5 ib] 8086,SM,LOCK
|
||||
SUB rm16,imm [mi: hle o16 81+s /5 ibw] 8086,SM,LOCK
|
||||
SUB rm32,imm [mi: hle o32 81+s /5 ibd] 386,SM,LOCK
|
||||
SUB rm64,imm [mi: hle o64 81+s /5 ibd,s] X64,SM,LOCK
|
||||
SUB rm16,sbyteword [mi: hle o16 83 /5 ib,s] 8086,SM,LOCK,ND
|
||||
SUB rm16,imm [mi: hle o16 81 /5 iw] 8086,SM,LOCK
|
||||
SUB rm32,sbytedword [mi: hle o32 83 /5 ib,s] 386,SM,LOCK,ND
|
||||
SUB rm32,imm [mi: hle o32 81 /5 id] 386,SM,LOCK
|
||||
SUB rm64,sbytedword [mi: hle o64 83 /5 ib,s] X64,SM,LOCK,ND
|
||||
SUB rm64,imm [mi: hle o64 81 /5 id,s] X64,SM,LOCK
|
||||
SUB mem,imm8 [mi: hle 80 /5 ib] 8086,SM,LOCK
|
||||
SUB mem,imm16 [mi: hle o16 81+s /5 ibw] 8086,SM,LOCK
|
||||
SUB mem,imm32 [mi: hle o32 81+s /5 ibd] 386,SM,LOCK
|
||||
SUB mem,sbyteword16 [mi: hle o16 83 /5 ib,s] 8086,SM,LOCK,ND
|
||||
SUB mem,imm16 [mi: hle o16 81 /5 iw] 8086,SM,LOCK
|
||||
SUB mem,sbytedword32 [mi: hle o32 83 /5 ib,s] 386,SM,LOCK,ND
|
||||
SUB mem,imm32 [mi: hle o32 81 /5 id] 386,SM,LOCK
|
||||
SUB rm8,imm [mi: hle 82 /5 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
SVDC mem80,reg_sreg [mr: 0f 78 /r] 486,CYRIX,SMM
|
||||
SVLDT mem80 [m: 0f 7a /0] 486,CYRIX,SMM,ND
|
||||
|
|
@ -1309,11 +1349,11 @@ TEST reg64,mem [rm: o64 85 /r] X64,SM
|
|||
TEST reg_al,imm [-i: a8 ib] 8086,SM
|
||||
TEST reg_ax,imm [-i: o16 a9 iw] 8086,SM
|
||||
TEST reg_eax,imm [-i: o32 a9 id] 386,SM
|
||||
TEST reg_rax,imm [-i: o64 a9 idx] X64,SM
|
||||
TEST reg_rax,imm [-i: o64 a9 id,s] X64,SM
|
||||
TEST rm8,imm [mi: f6 /0 ib] 8086,SM
|
||||
TEST rm16,imm [mi: o16 f7 /0 iw] 8086,SM
|
||||
TEST rm32,imm [mi: o32 f7 /0 id] 386,SM
|
||||
TEST rm64,imm [mi: o64 f7 /0 idx] X64,SM
|
||||
TEST rm64,imm [mi: o64 f7 /0 id,s] X64,SM
|
||||
TEST mem,imm8 [mi: f6 /0 ib] 8086,SM
|
||||
TEST mem,imm16 [mi: o16 f7 /0 iw] 8086,SM
|
||||
TEST mem,imm32 [mi: o32 f7 /0 id] 386,SM
|
||||
|
|
@ -1399,23 +1439,28 @@ XOR reg32,mem [rm: o32 33 /r] 386,SM
|
|||
XOR reg32,reg32 [rm: o32 33 /r] 386
|
||||
XOR reg64,mem [rm: o64 33 /r] X64,SM
|
||||
XOR reg64,reg64 [rm: o64 33 /r] X64
|
||||
XOR rm16,imm8 [mi: hle o16 83 /6 ibx] 8086,LOCK
|
||||
XOR rm32,imm8 [mi: hle o32 83 /6 ibx] 386,LOCK
|
||||
XOR rm64,imm8 [mi: hle o64 83 /6 ibx] X64,LOCK
|
||||
XOR rm16,imm8 [mi: hle o16 83 /6 ib,s] 8086,LOCK
|
||||
XOR rm32,imm8 [mi: hle o32 83 /6 ib,s] 386,LOCK
|
||||
XOR rm64,imm8 [mi: hle o64 83 /6 ib,s] X64,LOCK
|
||||
XOR reg_al,imm [-i: 34 ib] 8086,SM
|
||||
XOR reg_ax,sbyte16 [mi: o16 83 /6 ibx] 8086,SM
|
||||
XOR reg_ax,sbyteword [mi: o16 83 /6 ib,s] 8086,SM,ND
|
||||
XOR reg_ax,imm [-i: o16 35 iw] 8086,SM
|
||||
XOR reg_eax,sbyte32 [mi: o32 83 /6 ibx] 386,SM
|
||||
XOR reg_eax,sbytedword [mi: o32 83 /6 ib,s] 386,SM,ND
|
||||
XOR reg_eax,imm [-i: o32 35 id] 386,SM
|
||||
XOR reg_rax,sbyte64 [mi: o64 83 /6 ibx] X64,SM
|
||||
XOR reg_rax,imm [-i: o64 35 idx] X64,SM
|
||||
XOR reg_rax,sbytedword [mi: o64 83 /6 ib,s] X64,SM,ND
|
||||
XOR reg_rax,imm [-i: o64 35 id,s] X64,SM
|
||||
XOR rm8,imm [mi: hle 80 /6 ib] 8086,SM,LOCK
|
||||
XOR rm16,imm [mi: hle o16 81+s /6 ibw] 8086,SM,LOCK
|
||||
XOR rm32,imm [mi: hle o32 81+s /6 ibd] 386,SM,LOCK
|
||||
XOR rm64,imm [mi: hle o64 81+s /6 ibd,s] X64,SM,LOCK
|
||||
XOR rm16,sbyteword [mi: hle o16 83 /6 ib,s] 8086,SM,LOCK,ND
|
||||
XOR rm16,imm [mi: hle o16 81 /6 iw] 8086,SM,LOCK
|
||||
XOR rm32,sbytedword [mi: hle o32 83 /6 ib,s] 386,SM,LOCK,ND
|
||||
XOR rm32,imm [mi: hle o32 81 /6 id] 386,SM,LOCK
|
||||
XOR rm64,sbytedword [mi: hle o64 83 /6 ib,s] X64,SM,LOCK,ND
|
||||
XOR rm64,imm [mi: hle o64 81 /6 id,s] X64,SM,LOCK
|
||||
XOR mem,imm8 [mi: hle 80 /6 ib] 8086,SM,LOCK
|
||||
XOR mem,imm16 [mi: hle o16 81+s /6 ibw] 8086,SM,LOCK
|
||||
XOR mem,imm32 [mi: hle o32 81+s /6 ibd] 386,SM,LOCK
|
||||
XOR mem,sbyteword16 [mi: hle o16 83 /6 ib,s] 8086,SM,LOCK,ND
|
||||
XOR mem,imm16 [mi: hle o16 81 /6 iw] 8086,SM,LOCK
|
||||
XOR mem,sbytedword32 [mi: hle o32 83 /6 ib,s] 386,SM,LOCK,ND
|
||||
XOR mem,imm32 [mi: hle o32 81 /6 id] 386,SM,LOCK
|
||||
XOR rm8,imm [mi: hle 82 /6 ib] 8086,SM,LOCK,ND,NOLONG
|
||||
CMOVcc reg16,mem [rm: o16 0f 40+c /r] P6,SM
|
||||
CMOVcc reg16,reg16 [rm: o16 0f 40+c /r] P6
|
||||
|
|
|
|||
38
insns.pl
38
insns.pl
|
|
@ -439,13 +439,8 @@ sub format_insn($$$$$) {
|
|||
@opx = ();
|
||||
foreach $opp (split(/\|/, $op)) {
|
||||
@oppx = ();
|
||||
if ($opp =~ /^(.*[^\d])(8|16|32|64|80|128|256)$/) {
|
||||
my $ox = $1;
|
||||
my $on = $2;
|
||||
if ($ox !~ /^(sbyte|sdword|udword)$/) {
|
||||
$opp = $ox;
|
||||
push(@oppx, "bits$on");
|
||||
}
|
||||
if ($opp =~ s/(?<=\D)(8|16|32|64|80|128|256)$//) {
|
||||
push(@oppx, "bits$1");
|
||||
}
|
||||
$opp =~ s/^mem$/memory/;
|
||||
$opp =~ s/^memory_offs$/mem_offs/;
|
||||
|
|
@ -670,29 +665,20 @@ sub byte_code_compile($$) {
|
|||
my $opex;
|
||||
|
||||
my %imm_codes = (
|
||||
'ib,s' => 014, # Signed imm8
|
||||
'ib' => 020, # imm8
|
||||
'ib,u' => 024, # Unsigned imm8
|
||||
'iw' => 030, # imm16
|
||||
'ibx' => 0274, # imm8 sign-extended to opsize
|
||||
'ib,s' => 0274, # imm8 sign-extended to opsize or bits
|
||||
'iwd' => 034, # imm16 or imm32, depending on opsize
|
||||
'id' => 040, # imm32
|
||||
'idx' => 0254, # imm32 extended to 64 bits
|
||||
'iwdq' => 044, # imm16/32/64, depending on opsize
|
||||
'id,s' => 0254, # imm32 sign-extended to 64 bits
|
||||
'iwdq' => 044, # imm16/32/64, depending on addrsize
|
||||
'rel8' => 050,
|
||||
'iq' => 054,
|
||||
'rel16' => 060,
|
||||
'rel' => 064, # 16 or 32 bit relative operand
|
||||
'rel32' => 070,
|
||||
'seg' => 074,
|
||||
'ibw' => 0140, # imm16 that can be bytified
|
||||
'ibd' => 0150, # imm32 that can be bytified
|
||||
'ibd,s' => 0250 # imm32 that can be bytified, sign extended to 64 bits
|
||||
);
|
||||
my %imm_codes_bytifiers = (
|
||||
'ibw' => 0144,
|
||||
'ibd' => 0154,
|
||||
'ibd,s' => 0154
|
||||
);
|
||||
my %plain_codes = (
|
||||
'o16' => 0320, # 16-bit operand size
|
||||
|
|
@ -877,12 +863,6 @@ sub byte_code_compile($$) {
|
|||
}
|
||||
push(@codes, 05) if ($oppos{$last_imm} & 4);
|
||||
push(@codes, $imm_codes{$op} + ($oppos{$last_imm} & 3));
|
||||
if (defined $imm_codes_bytifiers{$op}) {
|
||||
if (!defined($s_pos)) {
|
||||
die "$fname: $line: $op without a +s byte\n";
|
||||
}
|
||||
$codes[$s_pos] += $imm_codes_bytifiers{$op};
|
||||
}
|
||||
$prefix_ok = 0;
|
||||
} elsif ($op eq '/is4') {
|
||||
if (!defined($oppos{'s'})) {
|
||||
|
|
@ -905,14 +885,6 @@ sub byte_code_compile($$) {
|
|||
}
|
||||
push(@codes, 0173, ($oppos{'s'} << 4) + $imm);
|
||||
$prefix_ok = 0;
|
||||
} elsif ($op =~ /^([0-9a-f]{2})\+s$/) {
|
||||
if (!defined($oppos{'i'})) {
|
||||
die "$fname: $line: $op without 'i' operand\n";
|
||||
}
|
||||
$s_pos = scalar @codes;
|
||||
push(@codes, 05) if ($oppos{'i'} & 4);
|
||||
push(@codes, $oppos{'i'} & 3, hex $1);
|
||||
$prefix_ok = 0;
|
||||
} elsif ($op =~ /^([0-9a-f]{2})\+c$/) {
|
||||
push(@codes, 0330, hex $1);
|
||||
$prefix_ok = 0;
|
||||
|
|
|
|||
17
opflags.h
17
opflags.h
|
|
@ -226,17 +226,12 @@ typedef uint64_t opflags_t;
|
|||
/* memory which matches any type of r/m operand */
|
||||
#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM)
|
||||
|
||||
/* special type of immediate operand */
|
||||
#define UNITY (GEN_SUBCLASS(1) | IMMEDIATE) /* for shift/rotate instructions */
|
||||
#define SBYTE16 (GEN_SUBCLASS(2) | IMMEDIATE) /* for op r16,immediate instrs. */
|
||||
#define SBYTE32 (GEN_SUBCLASS(3) | IMMEDIATE) /* for op r32,immediate instrs. */
|
||||
#define SBYTE64 (GEN_SUBCLASS(4) | IMMEDIATE) /* for op r64,immediate instrs. */
|
||||
#define SDWORD64 (GEN_SUBCLASS(5) | IMMEDIATE) /* for op r64,simm32 instrs. */
|
||||
#define UDWORD64 (GEN_SUBCLASS(0) | IMMEDIATE) /* for op r64,uimm32 instrs. */
|
||||
|
||||
#define BYTENESS (GEN_SUBCLASS(2) | \
|
||||
GEN_SUBCLASS(3) | \
|
||||
GEN_SUBCLASS(4)) /* for testing for byteness */
|
||||
/* special immediate values */
|
||||
#define UNITY (GEN_SUBCLASS(0) | IMMEDIATE) /* operand equals 1 */
|
||||
#define SBYTEWORD (GEN_SUBCLASS(1) | IMMEDIATE) /* operand is in the range -128..127 mod 2^16 */
|
||||
#define SBYTEDWORD (GEN_SUBCLASS(2) | IMMEDIATE) /* operand is in the range -128..127 mod 2^32 */
|
||||
#define SDWORD (GEN_SUBCLASS(3) | IMMEDIATE) /* operand is in the range -0x80000000..0x7FFFFFFF */
|
||||
#define UDWORD (GEN_SUBCLASS(4) | IMMEDIATE) /* operand is in the range 0..0xFFFFFFFF */
|
||||
|
||||
/* special flags */
|
||||
#define SAME_AS GEN_SPECIAL(0)
|
||||
|
|
|
|||
28
parser.c
28
parser.c
|
|
@ -853,7 +853,7 @@ is_expression:
|
|||
if(optimizing >= 0 && !(result->oprs[operand].type & STRICT)) {
|
||||
/* Be optimistic */
|
||||
result->oprs[operand].type |=
|
||||
SBYTE16 | SBYTE32 | SBYTE64 | UDWORD64 | SDWORD64;
|
||||
UNITY | SBYTEWORD | SBYTEDWORD | UDWORD | SDWORD;
|
||||
}
|
||||
} else if (is_reloc(value)) { /* it's immediate */
|
||||
result->oprs[operand].type |= IMMEDIATE;
|
||||
|
|
@ -862,25 +862,19 @@ is_expression:
|
|||
result->oprs[operand].wrt = reloc_wrt(value);
|
||||
|
||||
if (is_simple(value)) {
|
||||
if (reloc_value(value) == 1)
|
||||
uint64_t n = reloc_value(value);
|
||||
if (n == 1)
|
||||
result->oprs[operand].type |= UNITY;
|
||||
if (optimizing >= 0 &&
|
||||
!(result->oprs[operand].type & STRICT)) {
|
||||
int64_t v64 = reloc_value(value);
|
||||
int32_t v32 = (int32_t)v64;
|
||||
int16_t v16 = (int16_t)v32;
|
||||
|
||||
if (v64 >= -128 && v64 <= 127)
|
||||
result->oprs[operand].type |= SBYTE64;
|
||||
if (v32 >= -128 && v32 <= 127)
|
||||
result->oprs[operand].type |= SBYTE32;
|
||||
if (v16 >= -128 && v16 <= 127)
|
||||
result->oprs[operand].type |= SBYTE16;
|
||||
if ((uint64_t)v64 <= UINT64_C(0xffffffff))
|
||||
result->oprs[operand].type |= UDWORD64;
|
||||
if (v64 >= -INT64_C(0x80000000) &&
|
||||
v64 <= INT64_C(0x7fffffff))
|
||||
result->oprs[operand].type |= SDWORD64;
|
||||
if ((uint32_t) (n + 128) <= 255)
|
||||
result->oprs[operand].type |= SBYTEDWORD;
|
||||
if ((uint16_t) (n + 128) <= 255)
|
||||
result->oprs[operand].type |= SBYTEWORD;
|
||||
if (n <= 0xFFFFFFFF)
|
||||
result->oprs[operand].type |= UDWORD;
|
||||
if (n + 0x80000000 <= 0xFFFFFFFF)
|
||||
result->oprs[operand].type |= SDWORD;
|
||||
}
|
||||
}
|
||||
} else { /* it's a register */
|
||||
|
|
|
|||
Loading…
Reference in a new issue