MPX: Add MPX instructions
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
This commit is contained in:
Jin Kyu Song
parent
0bc288f8b9
commit
164d60740f
7 changed files with 61 additions and 2 deletions
23
assemble.c
23
assemble.c
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@ -42,6 +42,7 @@
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* \7 - add 4 to both the primary and the secondary operand number
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* \10..\13 - a literal byte follows in the code stream, to be added
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* to the register value of operand 0..3
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* \14..\17 - the position of index register operand in MIB (BND insns)
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* \20..\23 - a byte immediate operand, from operand 0..3
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* \24..\27 - a zero-extended byte immediate operand, from operand 0..3
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* \30..\33 - a word immediate operand, from operand 0..3
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@ -852,6 +853,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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enum ea_type eat;
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uint8_t hleok = 0;
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bool lockcheck = true;
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enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
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ins->rex = 0; /* Ensure REX is reset */
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eat = EA_SCALAR; /* Expect a scalar EA */
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@ -885,6 +887,11 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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codes++, length++;
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break;
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case4(014):
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/* this is an index reg of MIB operand */
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mib_index = opx->basereg;
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break;
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case4(020):
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case4(024):
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length++;
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@ -1184,6 +1191,17 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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}
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}
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/*
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* if a separate form of MIB (ICC style) is used,
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* the index reg info is merged into mem operand
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*/
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if (mib_index != R_none) {
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opy->indexreg = mib_index;
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opy->scale = 1;
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opy->hintbase = mib_index;
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opy->hinttype = EAH_NOTBASE;
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}
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if (process_ea(opy, &ea_data, bits,
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rfield, rflags, ins) != eat) {
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errfunc(ERR_NONFATAL, "invalid effective address");
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@ -1336,6 +1354,9 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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offset += 1;
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break;
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case4(014):
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break;
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case4(020):
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if (opx->offset < -256 || opx->offset > 255) {
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errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
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@ -2545,7 +2566,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
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}
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if (bt == it) /* convert EAX+2*EAX to 3*EAX */
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bt = -1, bx = 0, s++;
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if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
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if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
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/* make single reg base, unless hint */
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bt = it, bx = ix, it = -1, ix = 0;
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}
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21
insns.dat
21
insns.dat
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@ -4095,6 +4095,27 @@ VSCATTERPF1QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /6 ] AVX51
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VSCATTERPF1QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /6 ] AVX512PF,FUTURE
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PREFETCHWT1 mem8 [m: 0f 0d /2 ] FUTURE
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; MPX instructions
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BNDMK bndreg,mem32 [rm: o32 f3 0f 1b /r ] MPX,SD,FUTURE
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BNDMK bndreg,mem64 [rm: o64nw f3 0f 1b /r ] MPX,SQ,FUTURE
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BNDCL bndreg,rm32 [rm: o32 f3 0f 1a /r ] MPX,SD,FUTURE
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BNDCL bndreg,rm64 [rm: o64nw f3 0f 1a /r ] MPX,SQ,FUTURE
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BNDCU bndreg,rm32 [rm: o32 f2 0f 1a /r ] MPX,SD,FUTURE
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BNDCU bndreg,rm64 [rm: o64nw f2 0f 1a /r ] MPX,SQ,FUTURE
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BNDCN bndreg,rm32 [rm: o32 f2 0f 1b /r ] MPX,SD,FUTURE
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BNDCN bndreg,rm64 [rm: o64nw f2 0f 1b /r ] MPX,SQ,FUTURE
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BNDMOV bndreg,bndrm64 [rm: 66 0f 1a /r ] MPX,SQ,FUTURE
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BNDMOV bndreg,bndrm128 [rm: 66 0f 1a /r ] MPX,SO,FUTURE
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BNDMOV bndrm64,bndreg [mr: 66 0f 1b /r ] MPX,SQ,FUTURE
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BNDMOV bndrm128,bndreg [mr: 66 0f 1b /r ] MPX,SO,FUTURE
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BNDLDX bndreg,mem128 [rm: 0f 1a /r ] MPX,MIB,FUTURE
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BNDLDX bndreg,mem128,reg64 [rmx: 0f 1a /r ] MPX,MIB,FUTURE
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BNDSTX mem64,bndreg [mr: 0f 1b /r ] MPX,MIB,SQ,FUTURE
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BNDSTX mem64,reg32,bndreg [mxr: 0f 1b /r ] MPX,MIB,FUTURE
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BNDSTX mem64,bndreg,reg32 [mrx: 0f 1b /r ] MPX,MIB,FUTURE
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BNDSTX mem128,bndreg [mr: 0f 1b /r ] MPX,MIB,SO,FUTURE
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BNDSTX mem128,reg64,bndreg [mxr: 0f 1b /r ] MPX,MIB,FUTURE
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BNDSTX mem128,bndreg,reg64 [mrx: 0f 1b /r ] MPX,MIB,FUTURE
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;# Systematic names for the hinting nop instructions
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; These should be last in the file
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1
insns.h
1
insns.h
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@ -132,6 +132,7 @@ extern const uint8_t nasm_bytecodes[];
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#define IF_AVX512CD (0x1600000000UL|IF_AVX512) /* AVX-512 Conflict Detection insns */
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#define IF_AVX512ER (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */
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#define IF_AVX512PF (0x1800000000UL|IF_AVX512) /* AVX-512 Prefetch instructions */
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#define IF_MPX 0x1900000000UL /* MPX instructions */
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#define IF_INSMASK 0xFF00000000UL /* the mask for instruction set types */
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#define IF_PMASK 0xFF000000UL /* the mask for processor types */
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#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
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3
insns.pl
3
insns.pl
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@ -704,6 +704,7 @@ sub tupletype($) {
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# i = immediate
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# s = register field of is4/imz2 field
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# - = implicit (unencoded) operand
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# x = indeX register of mib. 014..017 bytecodes are used.
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#
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# For an operand that should be filled into more than one field,
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# enter it as e.g. "r+v".
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@ -843,6 +844,8 @@ sub byte_code_compile($$) {
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$opex = (($oppos{'m'} & 4) ? 06 : 0) |
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(($oppos{'r'} & 4) ? 05 : 0);
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push(@codes, $opex) if ($opex);
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# if mib is composed with two separate operands - ICC style
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push(@codes, 014 + ($oppos{'x'} & 3)) if (defined($oppos{'x'}));
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push(@codes, 0100 + (($oppos{'m'} & 3) << 3) + ($oppos{'r'} & 3));
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$prefix_ok = 0;
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} elsif ($op =~ m:^/([0-7])$:) {
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@ -163,6 +163,7 @@
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#define REG_CLASS_RM_YMM GEN_REG_CLASS(6)
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#define REG_CLASS_RM_ZMM GEN_REG_CLASS(7)
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#define REG_CLASS_OPMASK GEN_REG_CLASS(8)
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#define REG_CLASS_BND GEN_REG_CLASS(9)
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#define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op)))
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#define is_reg_class(class, reg) is_class((class), nasm_reg_flags[(reg)])
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@ -196,6 +197,8 @@
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#define OPMASK0 (GEN_SUBCLASS(1) | REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register zero (k0) */
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#define RM_K RM_OPMASK
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#define KREG OPMASKREG
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#define RM_BND ( REG_CLASS_BND | REGMEM) /* Bounds operand */
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#define BNDREG ( REG_CLASS_BND | REGMEM | REGISTER) /* Bounds register */
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#define REG_CDT ( REG_CLASS_CDT | BITS32 | REGISTER) /* CRn, DRn and TRn */
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#define REG_CREG (GEN_SUBCLASS(1) | REG_CLASS_CDT | BITS32 | REGISTER) /* CRn */
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#define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */
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@ -243,7 +246,7 @@
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#define ZMEM (GEN_SUBCLASS(5) | MEMORY) /* 512-bit vector SIB */
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/* memory which matches any type of r/m operand */
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#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM | RM_ZMM | RM_OPMASK)
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#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM | RM_ZMM | RM_OPMASK | RM_BND)
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/* special immediate values */
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#define UNITY (GEN_SUBCLASS(0) | IMMEDIATE) /* operand equals 1 */
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7
parser.c
7
parser.c
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@ -821,6 +821,13 @@ is_expression:
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process_size_override(result, op);
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i = stdscan(NULL, &tokval);
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}
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/* when a comma follows an opening bracket - [ , eax*4] */
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if (i == ',') {
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/* treat as if there is a zero displacement virtually */
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tokval.t_type = TOKEN_NUM;
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tokval.t_integer = 0;
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stdscan_set(stdscan_get() - 1); /* rewind the comma */
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}
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} else { /* immediate operand, or register */
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mref = false;
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bracket = false; /* placate optimisers */
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3
regs.dat
3
regs.dat
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@ -130,3 +130,6 @@ zmm1-31 ZMMREG zmmreg 1
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# Opmask registers
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k0 OPMASK0 opmaskreg 0
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k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT
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# Bounds registers
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bnd0-3 BNDREG bndreg 0
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