Add support for the new instructions in Prescott
This commit is contained in:
H. Peter Anvin
parent
8fa0d037f3
commit
10101f26bc
6 changed files with 39 additions and 2 deletions
4
disasm.c
4
disasm.c
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@ -43,8 +43,12 @@ static int whichreg(long regflags, int regval)
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return R_AX;
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if (!(REG_EAX & ~regflags))
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return R_EAX;
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if (!(REG_DL & ~regflags))
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return R_DL;
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if (!(REG_DX & ~regflags))
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return R_DX;
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if (!(REG_EDX & ~regflags))
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return R_EDX;
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if (!(REG_CL & ~regflags))
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return R_CL;
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if (!(REG_CX & ~regflags))
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28
insns.dat
28
insns.dat
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@ -318,6 +318,9 @@ FIST mem16 \300\1\xDF\202 8086,FPU
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FISTP mem32 \300\1\xDB\203 8086,FPU
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FISTP mem16 \300\1\xDF\203 8086,FPU
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FISTP mem64 \300\1\xDF\207 8086,FPU
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FISTTP mem32 \300\1\xDD\201 PRESCOTT,FPU
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FISTTP mem16 \300\1\xDB\201 PRESCOTT,FPU
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FISTTP mem64 \300\1\xDF\201 PRESCOTT,FPU
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FISUB mem32 \300\1\xDA\204 8086,FPU
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FISUB mem16 \300\1\xDE\204 8086,FPU
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FISUBR mem32 \300\1\xDA\205 8086,FPU
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@ -563,6 +566,8 @@ LSS reg32,mem \321\301\2\x0F\xB2\110 386
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LTR mem \300\1\x0F\17\203 286,PROT,PRIV
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LTR mem16 \300\1\x0F\17\203 286,PROT,PRIV
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LTR reg16 \1\x0F\17\203 286,PROT,PRIV
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MONITOR void \3\x0F\x01\xC8 PRESCOTT
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MONITOR reg_eax,reg_ecx,reg_edx \3\x0F\x01\xC8 PRESCOTT,ND
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MOV mem,reg_sreg \300\1\x8C\101 8086,SM
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MOV reg16,reg_sreg \320\1\x8C\101 8086
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MOV reg32,reg_sreg \321\1\x8C\101 386
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@ -624,6 +629,8 @@ MOVZX reg32,rm16 \321\301\2\x0F\xB7\110 386
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MUL rm8 \300\1\xF6\204 8086
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MUL rm16 \320\300\1\xF7\204 8086
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MUL rm32 \321\300\1\xF7\204 386
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MWAIT void \3\x0F\x01\xC9 PRESCOTT
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MWAIT reg_eax,reg_ecx \3\x0F\x01\xC9 PRESCOTT,ND
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NEG rm8 \300\1\xF6\203 8086
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NEG rm16 \320\300\1\xF7\203 8086
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NEG rm32 \321\300\1\xF7\203 386
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@ -1641,3 +1648,24 @@ UNPCKLPD xmmreg,xmmreg \3\x66\x0F\x14\110 WILLAMET
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UNPCKLPD xmmreg,mem \301\3\x66\x0F\x14\110 WILLAMETTE,SSE2,SM
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XORPD xmmreg,xmmreg \3\x66\x0F\x57\110 WILLAMETTE,SSE2
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XORPD xmmreg,mem \301\3\x66\x0F\x57\110 WILLAMETTE,SSE2,SM
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; Prescott New Instructions (SSE3)
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ADDSUBPD xmmreg,mem \301\3\x66\x0F\xD0\110 PRESCOTT,SSE3,SM
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ADDSUBPD xmmreg,xmmreg \3\x66\x0F\xD0\110 PRESCOTT,SSE3
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ADDSUBPS xmmreg,mem \301\3\xF2\x0F\xD0\110 PRESCOTT,SSE3,SM
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ADDSUBPS xmmreg,xmmreg \3\xF2\x0F\xD0\110 PRESCOTT,SSE3
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HADDPD xmmreg,mem \301\3\x66\x0F\x7C\110 PRESCOTT,SSE3,SM
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HADDPD xmmreg,xmmreg \3\x66\x0F\x7C\110 PRESCOTT,SSE3
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HADDPS xmmreg,mem \301\3\xF2\x0F\x7C\110 PRESCOTT,SSE3,SM
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HADDPS xmmreg,xmmreg \3\xF2\x0F\x7C\110 PRESCOTT,SSE3
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HSUBPD xmmreg,mem \301\3\x66\x0F\x7D\110 PRESCOTT,SSE3,SM
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HSUBPD xmmreg,xmmreg \3\x66\x0F\x7D\110 PRESCOTT,SSE3
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HSUBPS xmmreg,mem \301\3\xF2\x0F\x7D\110 PRESCOTT,SSE3,SM
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HSUBPS xmmreg,xmmreg \3\xF2\x0F\x7D\110 PRESCOTT,SSE3
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LDDQU xmmreg,mem \3\xF2\x0F\xF0\110 PRESCOTT,SSE3
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MOVDDUP xmmreg,mem \301\3\xF2\x0F\x12\110 PRESCOTT,SSE3
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MOVDDUP xmmreg,xmmreg \3\xF2\x0F\x12\110 PRESCOTT,SSE3
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MOVSHDUP xmmreg,mem \301\3\xF3\x0F\x16\110 PRESCOTT,SSE3
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MOVSHDUP xmmreg,xmmreg \3\xF3\x0F\x16\110 PRESCOTT,SSE3
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MOVSLDUP xmmreg,mem \301\3\xF3\x0F\x12\110 PRESCOTT,SSE3
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MOVSLDUP xmmreg,xmmreg \3\xF3\x0F\x12\110 PRESCOTT,SSE3
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2
insns.h
2
insns.h
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@ -77,6 +77,7 @@ struct itemplate {
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#define IF_3DNOW 0x00008000UL /* it's a 3DNow! instruction */
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#define IF_SSE 0x00010000UL /* it's a SSE (KNI, MMX2) instruction */
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#define IF_SSE2 0x00020000UL /* it's a SSE2 instruction */
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#define IF_SSE3 0x00040000UL /* it's a SSE3 (PNI) instruction */
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#define IF_PMASK 0xFF000000UL /* the mask for processor types */
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#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
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/* also the highest possible processor */
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@ -90,6 +91,7 @@ struct itemplate {
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#define IF_P6 0x06000000UL /* P6 instruction */
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#define IF_KATMAI 0x07000000UL /* Katmai instructions */
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#define IF_WILLAMETTE 0x08000000UL /* Willamette instructions */
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#define IF_PRESCOTT 0x09000000UL /* Prescott instructions */
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#define IF_IA64 0x0F000000UL /* IA64 instructions */
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#define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */
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#define IF_AMD 0x20000000UL /* AMD-specific instruction */
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1
nasm.c
1
nasm.c
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@ -1635,6 +1635,7 @@ static unsigned long get_cpu (char *value)
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!nasm_stricmp(value, "katmai") ) return IF_KATMAI;
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if (!nasm_stricmp(value, "p4") || /* is this right? -- jrc */
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!nasm_stricmp(value, "willamette") ) return IF_WILLAMETTE;
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if (!nasm_stricmp(value, "prescott") ) return IF_PRESCOTT;
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if (!nasm_stricmp(value, "ia64") ||
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!nasm_stricmp(value, "ia-64") ||
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!nasm_stricmp(value, "itanium") ||
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2
nasm.h
2
nasm.h
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@ -410,7 +410,9 @@ enum {
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#define REG_CL 0x00221001L /* REG_COUNT | BITSxx */
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#define REG_CX 0x00221002L /* ditto */
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#define REG_ECX 0x00221004L /* another one */
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#define REG_DL 0x00241001L
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#define REG_DX 0x00241002L
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#define REG_EDX 0x00241004L
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#define REG_SREG 0x00081002L /* any segment register */
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#define REG_CS 0x01081002L /* CS */
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#define REG_DESS 0x02081002L /* DS, ES, SS (non-CS 86 registers) */
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4
regs.dat
4
regs.dat
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@ -19,10 +19,10 @@ cl REG_CL reg8 1
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ch REG8 reg8 5
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cx REG_CX reg16 1
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ecx REG_ECX reg32 1
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dl REG8 reg8 2
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dl REG_DL reg8 2
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dh REG8 reg8 6
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dx REG_DX reg16 2
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edx REG32 reg32 2
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edx REG_EDX reg32 2
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sp REG16 reg16 4
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esp REG32 reg32 4
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bp REG16 reg16 5
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