nasm/test/clzero.asm

	bits 16

	clzero
	clzero ax
	clzero eax
%ifdef ERROR
	clzero rax
%endif

	bits 32

	clzero
	clzero ax
	clzero eax
%ifdef ERROR
	clzero rax
%endif

	bits 64

	clzero
%ifdef ERROR
	clzero ax
%endif
	clzero eax
	clzero rax
insns.dat: accept explicit ax/eax/rax operand to CLZERO AMD documents this instruction with an rax operand. The error behavior implies this is an address-size-sensitive instruction. Add support for specifying the explicit operand, but consistent with normal ndisasm behavior, don't disassemble the implicit operand. Signed-off-by: H. Peter Anvin <hpa@zytor.com> 2018-12-23 01:50:26 +00:00			`bits 16`

			`clzero`
			`clzero ax`
			`clzero eax`
			`%ifdef ERROR`
			`clzero rax`
			`%endif`

			`bits 32`

			`clzero`
			`clzero ax`
			`clzero eax`
			`%ifdef ERROR`
			`clzero rax`
			`%endif`

			`bits 64`

			`clzero`
			`%ifdef ERROR`
			`clzero ax`
			`%endif`
			`clzero eax`
			`clzero rax`