6aa5370ccc
Partial SVE modes can be picked up and used by the vector_size(N)
attribute.[*] This means that we need to cope with arguments and return
values with partial SVE modes, which previously triggered asserts like:
/* Generic vectors that map to SVE modes with -msve-vector-bits=N are
passed by reference, not by value. */
gcc_assert (!aarch64_sve_mode_p (mode));
The ABI for these types is fixed from pre-SVE days, and must in any case
be the same for all -msve-vector-bits=N values. All we need to do is
ensure that the vectors are passed and returned in the traditional way.
[*] Advanced SIMD always wins for 64-bit and 128-bit vectors though.
2019-12-19 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_function_value_1): New function,
split out from...
(aarch64_function_value): ...here. Handle partial SVE modes by
pretending that they have the associated/traditional integer mode,
then wrap the result in the real mode.
(aarch64_layout_arg): Take an orig_mode argument and pass it to
aarch64_function_arg_alignment. Handle partial SVE modes analogously
to aarch64_function_value.
(aarch64_function_arg): Update call accordingly.
(aarch64_function_arg_advance): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/pcs/gnu_vectors_3.c: New test.
From-SVN: r279571
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