2f03b10da8
This test has been failing since r15-1619-g3b9b8d6cfdf593, which made IRA prefer a call-clobbered register over a call-preserved register for mem1 (the second load). In this particular case, that just forces the variable p3 to be allocated to a call-preserved register instead, leading to an extra predicate move from p3 to that register. However, it was really pot luck that this worked before. Each argument is used exactly once, so there isn't an obvious colouring order. And mem0 and mem1 are passed by indirect reference, so they are not REG_EQUIV to a stack slot in the way that some memory arguments are. IIRC, the test was the result of some experimentation, and so I think the best fix is to rework it to try to make it less sensitive to RA decisions. This patch does that by enabling scheduling for the function and using both memory arguments in the same instruction. This gets rid of the distracting prologue and epilogue code and restricts the test to the PCS parts. gcc/testsuite/ PR testsuite/116604 * gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Enable scheduling and use both memory arguments in the same instruction. Expect no prologue and epilogue code. |
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