2a7f490494
This patch would like to implement the sssub for vector signed integer.
Form 1:
#define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T minus = (UT)x - (UT)y; \
out[i] = (x ^ y) >= 0 \
? minus \
: (minus ^ x) >= 0 \
? minus \
: x < 0 ? MIN : MAX; \
} \
}
DEF_VEC_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
Before this patch:
28 │ vle8.v v1,0(a1)
29 │ vle8.v v2,0(a2)
30 │ sub a3,a3,a5
31 │ add a1,a1,a5
32 │ add a2,a2,a5
33 │ vsra.vi v4,v1,7
34 │ vsub.vv v3,v1,v2
35 │ vxor.vv v2,v1,v2
36 │ vxor.vv v0,v1,v3
37 │ vmslt.vi v2,v2,0
38 │ vmslt.vi v0,v0,0
39 │ vmand.mm v0,v0,v2
40 │ vxor.vv v3,v4,v5,v0.t
41 │ vse8.v v3,0(a0)
42 │ add a0,a0,a5
After this patch:
25 │ vle8.v v1,0(a1)
26 │ vle8.v v2,0(a2)
27 │ sub a3,a3,a5
28 │ add a1,a1,a5
29 │ add a2,a2,a5
30 │ vssub.vv v1,v1,v2
31 │ vse8.v v1,0(a0)
32 │ add a0,a0,a5
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/autovec.md (sssub<mode>3): Add new pattern for
signed SAT_SUB.
* config/riscv/riscv-protos.h (expand_vec_sssub): Add new func
decl to expand sssub to vssub.
* config/riscv/riscv-v.cc (expand_vec_sssub): Add new func
impl to expand sssub to vssub.
Signed-off-by: Pan Li <pan2.li@intel.com>
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