324 lines
8.8 KiB
C
324 lines
8.8 KiB
C
/* PA-RISC sync libfunc support.
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Copyright (C) 2008-2025 Free Software Foundation, Inc.
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Based on code contributed by CodeSourcery for ARM EABI Linux.
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Modifications for PA Linux by Helge Deller <deller@gmx.de>
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Revised for general use by John David Anglin <danglin@gcc.gnu.org>
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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typedef unsigned char u8;
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typedef short unsigned int u16;
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typedef unsigned int u32;
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#ifdef __LP64__
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typedef long unsigned int u64;
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#else
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typedef long long unsigned int u64;
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#endif
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/* PA-RISC 2.0 supports out-of-order execution for loads and stores.
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Thus, we need to synchonize memory accesses. For more info, see:
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"Advanced Performance Features of the 64-bit PA-8000" by Doug Hunt. */
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typedef volatile int __attribute__((aligned (16))) ldcw_t;
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static ldcw_t __atomicity_lock = 1;
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/* We want default visibility for the sync routines. */
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#undef VISIBILITY
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#if defined(__hpux__) && !defined(__LP64__)
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#define VISIBILITY
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#else
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#define VISIBILITY __attribute__ ((visibility ("default")))
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#endif
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/* Perform ldcw operation in cache when possible. The ldcw instruction
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is a full barrier. */
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#ifndef _PA_LDCW_INSN
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# ifdef _PA_RISC2_0
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# define _PA_LDCW_INSN "ldcw,co"
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# else
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# define _PA_LDCW_INSN "ldcw"
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# endif
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#endif
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static inline void
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__sync_spin_lock (void)
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{
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ldcw_t *lock = &__atomicity_lock;
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int tmp;
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__asm__ __volatile__ (_PA_LDCW_INSN " 0(%1),%0\n\t"
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"cmpib,<>,n 0,%0,.+20\n\t"
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"ldw,ma 0(%1),%0\n\t"
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"cmpib,<> 0,%0,.-12\n\t"
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"nop\n\t"
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"b,n .-12"
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: "=&r" (tmp)
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: "r" (lock)
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: "memory");
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}
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static inline void
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__sync_spin_unlock (void)
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{
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ldcw_t *lock = &__atomicity_lock;
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int tmp = 1;
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/* Use ordered store for release. */
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__asm__ __volatile__ ("stw,ma %1,0(%0)"
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: : "r" (lock), "r" (tmp) : "memory");
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}
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/* Load value with an atomic processor load if possible. */
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#define ATOMIC_LOAD(TYPE, WIDTH) \
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static inline TYPE \
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atomic_load_##WIDTH (volatile void *ptr) \
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{ \
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return *(volatile TYPE *)ptr; \
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}
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#if defined(__LP64__) || defined(__SOFTFP__)
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ATOMIC_LOAD (u64, 8)
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#else
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static inline u64
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atomic_load_8 (volatile void *ptr)
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{
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u64 result;
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double tmp;
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asm volatile ("{fldds|fldd} 0(%2),%1\n\t"
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"{fstds|fstd} %1,-16(%%sp)\n\t"
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"{ldws|ldw} -16(%%sp),%0\n\t"
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"{ldws|ldw} -12(%%sp),%R0"
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: "=r" (result), "=f" (tmp) : "r" (ptr): "memory");
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return result;
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}
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#endif
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ATOMIC_LOAD (u32, 4)
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ATOMIC_LOAD (u16, 2)
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ATOMIC_LOAD (u8, 1)
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/* Store value with an atomic processor store if possible. */
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#define ATOMIC_STORE(TYPE, WIDTH) \
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static inline void \
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atomic_store_##WIDTH (volatile void *ptr, TYPE value) \
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{ \
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*(volatile TYPE *)ptr = value; \
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}
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#if defined(__LP64__) || defined(__SOFTFP__)
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ATOMIC_STORE (u64, 8)
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#else
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static inline void
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atomic_store_8 (volatile void *ptr, u64 value)
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{
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double tmp;
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asm volatile ("stws|stw} %2,-16(%%sp)\n\t"
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"{stws|stw} %R2,-12(%%sp)\n\t"
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"{fldds|fldd} -16(%%sp),%1\n\t"
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"{fstds|fstd} %1,0(%0)"
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: "=m" (ptr), "=&f" (tmp) : "r" (value): "memory");
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}
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#endif
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ATOMIC_STORE (u32, 4)
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ATOMIC_STORE (u16, 2)
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ATOMIC_STORE (u8, 1)
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#define FETCH_AND_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH) \
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TYPE VISIBILITY \
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__sync_fetch_and_##OP##_##WIDTH (volatile void *ptr, TYPE val) \
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{ \
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TYPE tmp, newval; \
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\
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__sync_spin_lock(); \
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tmp = atomic_load_##WIDTH (ptr); \
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newval = PFX_OP (tmp INF_OP val); \
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atomic_store_##WIDTH (ptr, newval); \
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__sync_spin_unlock(); \
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\
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return tmp; \
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}
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FETCH_AND_OP (add, , +, u64, 8)
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FETCH_AND_OP (sub, , -, u64, 8)
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FETCH_AND_OP (or, , |, u64, 8)
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FETCH_AND_OP (and, , &, u64, 8)
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FETCH_AND_OP (xor, , ^, u64, 8)
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FETCH_AND_OP (nand, ~, &, u64, 8)
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FETCH_AND_OP (add, , +, u32, 4)
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FETCH_AND_OP (sub, , -, u32, 4)
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FETCH_AND_OP (or, , |, u32, 4)
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FETCH_AND_OP (and, , &, u32, 4)
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FETCH_AND_OP (xor, , ^, u32, 4)
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FETCH_AND_OP (nand, ~, &, u32, 4)
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FETCH_AND_OP (add, , +, u16, 2)
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FETCH_AND_OP (sub, , -, u16, 2)
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FETCH_AND_OP (or, , |, u16, 2)
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FETCH_AND_OP (and, , &, u16, 2)
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FETCH_AND_OP (xor, , ^, u16, 2)
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FETCH_AND_OP (nand, ~, &, u16, 2)
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FETCH_AND_OP (add, , +, u8, 1)
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FETCH_AND_OP (sub, , -, u8, 1)
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FETCH_AND_OP (or, , |, u8, 1)
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FETCH_AND_OP (and, , &, u8, 1)
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FETCH_AND_OP (xor, , ^, u8, 1)
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FETCH_AND_OP (nand, ~, &, u8, 1)
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#define OP_AND_FETCH(OP, PFX_OP, INF_OP, TYPE, WIDTH) \
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TYPE VISIBILITY \
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__sync_##OP##_and_fetch_##WIDTH (volatile void *ptr, TYPE val) \
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{ \
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TYPE tmp, newval; \
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\
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__sync_spin_lock(); \
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tmp = atomic_load_##WIDTH (ptr); \
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newval = PFX_OP (tmp INF_OP val); \
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atomic_store_##WIDTH (ptr, newval); \
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__sync_spin_unlock(); \
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\
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return newval; \
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}
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OP_AND_FETCH (add, , +, u64, 8)
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OP_AND_FETCH (sub, , -, u64, 8)
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OP_AND_FETCH (or, , |, u64, 8)
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OP_AND_FETCH (and, , &, u64, 8)
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OP_AND_FETCH (xor, , ^, u64, 8)
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OP_AND_FETCH (nand, ~, &, u64, 8)
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OP_AND_FETCH (add, , +, u32, 4)
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OP_AND_FETCH (sub, , -, u32, 4)
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OP_AND_FETCH (or, , |, u32, 4)
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OP_AND_FETCH (and, , &, u32, 4)
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OP_AND_FETCH (xor, , ^, u32, 4)
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OP_AND_FETCH (nand, ~, &, u32, 4)
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OP_AND_FETCH (add, , +, u16, 2)
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OP_AND_FETCH (sub, , -, u16, 2)
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OP_AND_FETCH (or, , |, u16, 2)
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OP_AND_FETCH (and, , &, u16, 2)
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OP_AND_FETCH (xor, , ^, u16, 2)
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OP_AND_FETCH (nand, ~, &, u16, 2)
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OP_AND_FETCH (add, , +, u8, 1)
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OP_AND_FETCH (sub, , -, u8, 1)
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OP_AND_FETCH (or, , |, u8, 1)
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OP_AND_FETCH (and, , &, u8, 1)
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OP_AND_FETCH (xor, , ^, u8, 1)
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OP_AND_FETCH (nand, ~, &, u8, 1)
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#define COMPARE_AND_SWAP(TYPE, WIDTH) \
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TYPE VISIBILITY \
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__sync_val_compare_and_swap_##WIDTH (volatile void *ptr, TYPE oldval, \
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TYPE newval) \
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{ \
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TYPE actual_oldval; \
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\
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__sync_spin_lock(); \
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actual_oldval = atomic_load_##WIDTH (ptr); \
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if (actual_oldval == oldval) \
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atomic_store_##WIDTH (ptr, newval); \
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__sync_spin_unlock(); \
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\
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return actual_oldval; \
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} \
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\
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_Bool VISIBILITY \
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__sync_bool_compare_and_swap_##WIDTH (volatile void *ptr, \
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TYPE oldval, TYPE newval) \
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{ \
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TYPE actual_oldval; \
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_Bool result; \
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\
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__sync_spin_lock(); \
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actual_oldval = atomic_load_##WIDTH (ptr); \
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result = (actual_oldval == oldval); \
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if (result) \
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atomic_store_##WIDTH (ptr, newval); \
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__sync_spin_unlock(); \
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\
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return result; \
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}
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COMPARE_AND_SWAP (u64, 8)
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COMPARE_AND_SWAP (u32, 4)
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COMPARE_AND_SWAP (u16, 2)
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COMPARE_AND_SWAP (u8, 1)
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#define SYNC_LOCK_TEST_AND_SET(TYPE, WIDTH) \
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TYPE VISIBILITY \
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__sync_lock_test_and_set_##WIDTH (volatile void *ptr, TYPE val) \
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{ \
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TYPE oldval; \
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\
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__sync_spin_lock(); \
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oldval = atomic_load_##WIDTH (ptr); \
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atomic_store_##WIDTH (ptr, val); \
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__sync_spin_unlock(); \
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\
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return oldval; \
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}
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SYNC_LOCK_TEST_AND_SET (u64, 8)
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SYNC_LOCK_TEST_AND_SET (u32, 4)
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SYNC_LOCK_TEST_AND_SET (u16, 2)
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SYNC_LOCK_TEST_AND_SET (u8, 1)
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#define SYNC_LOCK_RELEASE(TYPE, WIDTH) \
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void VISIBILITY \
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__sync_lock_release_##WIDTH (volatile void *ptr) \
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{ \
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TYPE val = 0; \
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\
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__sync_spin_lock(); \
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atomic_store_##WIDTH (ptr, val); \
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__sync_spin_unlock(); \
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}
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SYNC_LOCK_RELEASE (u64, 8)
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SYNC_LOCK_RELEASE (u32, 4)
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SYNC_LOCK_RELEASE (u16, 2)
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SYNC_LOCK_RELEASE (u8, 1)
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#define SYNC_LOCK_LOAD(TYPE, WIDTH) \
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TYPE VISIBILITY __sync_lock_load_##WIDTH (volatile void *); \
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TYPE VISIBILITY \
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__sync_lock_load_##WIDTH (volatile void *ptr) \
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{ \
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TYPE oldval; \
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\
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__sync_spin_lock(); \
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oldval = atomic_load_##WIDTH (ptr); \
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__sync_spin_unlock(); \
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\
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return oldval; \
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}
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SYNC_LOCK_LOAD (u64, 8)
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SYNC_LOCK_LOAD (u32, 4)
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SYNC_LOCK_LOAD (u16, 2)
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SYNC_LOCK_LOAD (u8, 1)
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