xtensa: Remove old broken tweak for leaf function
In the before-IRA era, ORDER_REGS_FOR_LOCAL_ALLOC was called for each function in Xtensa, and there was register allocation table reordering for leaf functions to compensate for the poor performance of local-alloc. Today the adjustment hook is still called via its alternative ADJUST_REG_ALLOC_ORDER, but it is only called once at the start of the IRA, and leaf_function_p() erroneously returns true and also gives no argument count. That straightforwardly misleads register allocation that all functions are always leaves with no arguments, which leads to inefficiencies in allocation results. Fortunately, IRA is smart enough than local-alloc to not need such assistance. This patch does away with the antiquated by removing the wreckage that no longer works. gcc/ChangeLog: * config/xtensa/xtensa-protos.h (order_regs_for_local_alloc): Rename to xtensa_adjust_reg_alloc_order. * config/xtensa/xtensa.cc (xtensa_adjust_reg_alloc_order): Ditto. And also remove code to reorder register numbers for leaf functions, rename the tables, and adjust the allocation order for the call0 ABI to use register A0 more. (xtensa_leaf_regs): Remove. * config/xtensa/xtensa.h (REG_ALLOC_ORDER): Cosmetics. (order_regs_for_local_alloc): Rename as the above. (LEAF_REGISTERS, LEAF_REG_REMAP, leaf_function): Remove.
This commit is contained in:
Takayuki 'January June' Suwa
Max Filippov
parent
a3b99b8460
commit
ff6c761710
3 changed files with 28 additions and 96 deletions
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@ -78,7 +78,7 @@ extern long compute_frame_size (poly_int64);
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extern bool xtensa_use_return_instruction_p (void);
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extern void xtensa_expand_prologue (void);
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extern void xtensa_expand_epilogue (bool);
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extern void order_regs_for_local_alloc (void);
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extern void xtensa_adjust_reg_alloc_order (void);
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extern enum reg_class xtensa_regno_to_class (int regno);
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extern HOST_WIDE_INT xtensa_initial_elimination_offset (int from, int to);
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extern const char **xtensa_get_config_strings (void);
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@ -107,18 +107,6 @@ struct GTY(()) machine_function
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rtx last_logues_a9_content;
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};
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/* Vector, indexed by hard register number, which contains 1 for a
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register that is allowable in a candidate for leaf function
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treatment. */
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const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
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{
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1
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};
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static void xtensa_option_override (void);
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static enum internal_test map_test_to_internal_test (enum rtx_code);
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static rtx gen_int_relational (enum rtx_code, rtx, rtx);
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@ -4140,58 +4128,25 @@ xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
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return NO_REGS;
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}
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/* Called once at the start of IRA, by ADJUST_REG_ALLOC_ORDER. */
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void
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order_regs_for_local_alloc (void)
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xtensa_adjust_reg_alloc_order (void)
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{
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if (!leaf_function_p ())
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{
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static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
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static const int reg_windowed_alloc_order[FIRST_PSEUDO_REGISTER] =
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REG_ALLOC_ORDER;
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static const int reg_nonleaf_alloc_order_call0[FIRST_PSEUDO_REGISTER] =
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{
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11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 12, 13, 14, 15,
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18,
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19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
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0, 1, 16, 17,
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35,
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};
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static const int reg_call0_alloc_order[FIRST_PSEUDO_REGISTER] =
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{
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9, 10, 11, 7, 6, 5, 4, 3, 2, 8, 0, 12, 13, 14, 15,
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18,
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19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
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1, 16, 17,
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35,
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};
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memcpy (reg_alloc_order, TARGET_WINDOWED_ABI ?
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reg_nonleaf_alloc_order : reg_nonleaf_alloc_order_call0,
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FIRST_PSEUDO_REGISTER * sizeof (int));
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}
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else
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{
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int i, num_arg_regs;
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int nxt = 0;
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/* Use the AR registers in increasing order (skipping a0 and a1)
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but save the incoming argument registers for a last resort. */
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num_arg_regs = crtl->args.info.arg_words;
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if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
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num_arg_regs = MAX_ARGS_IN_REGISTERS;
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for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
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reg_alloc_order[nxt++] = i + num_arg_regs;
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for (i = 0; i < num_arg_regs; i++)
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reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
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/* List the coprocessor registers in order. */
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for (i = 0; i < BR_REG_NUM; i++)
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reg_alloc_order[nxt++] = BR_REG_FIRST + i;
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/* List the FP registers in order for now. */
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for (i = 0; i < 16; i++)
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reg_alloc_order[nxt++] = FP_REG_FIRST + i;
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/* GCC requires that we list *all* the registers.... */
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reg_alloc_order[nxt++] = 0; /* a0 = return address */
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reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
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reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
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reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
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reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
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}
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memcpy (reg_alloc_order, TARGET_WINDOWED_ABI ?
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reg_windowed_alloc_order : reg_call0_alloc_order,
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FIRST_PSEUDO_REGISTER * sizeof (int));
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}
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@ -238,44 +238,21 @@ along with GCC; see the file COPYING3. If not see
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1, \
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}
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/* For non-leaf procedures on Xtensa processors, the allocation order
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is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
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want to use the lowest numbered registers first to minimize
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register window overflows. However, local-alloc is not smart
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enough to consider conflicts with incoming arguments. If an
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incoming argument in a2 is live throughout the function and
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local-alloc decides to use a2, then the incoming argument must
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either be spilled or copied to another register. To get around
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this, we define ADJUST_REG_ALLOC_ORDER to redefine
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reg_alloc_order for leaf functions such that lowest numbered
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registers are used first with the exception that the incoming
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argument registers are not used until after other register choices
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have been exhausted. */
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/* For the windowed register ABI on Xtensa processors, the allocation
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order is as specified below by REG_ALLOC_ORDER.
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For the call0 ABI, on the other hand, ADJUST_REG_ALLOC_ORDER hook
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will be called once at the start of IRA, replacing it with the
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appropriate one. */
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#define REG_ALLOC_ORDER \
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{ 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
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18, \
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19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
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0, 1, 16, 17, \
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35, \
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#define REG_ALLOC_ORDER \
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{ \
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8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
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18, \
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19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
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0, 1, 16, 17, \
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35, \
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}
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#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
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/* For Xtensa, the only point of this is to prevent GCC from otherwise
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giving preference to call-used registers. To minimize window
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overflows for the AR registers, we want to give preference to the
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lower-numbered AR registers. For other register files, which are
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not windowed, we still prefer call-used registers, if there are any. */
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extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
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#define LEAF_REGISTERS xtensa_leaf_regs
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/* For Xtensa, no remapping is necessary, but this macro must be
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defined if LEAF_REGISTERS is defined. */
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#define LEAF_REG_REMAP(REGNO) ((int) (REGNO))
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/* This must be declared if LEAF_REGISTERS is set. */
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extern int leaf_function;
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#define ADJUST_REG_ALLOC_ORDER xtensa_adjust_reg_alloc_order ()
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/* Internal macros to classify a register number. */
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