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RISC-V: Add --with-cmodel configure option

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Sometimes we want to use default cmodel other than medlow. Add a GCC
configure option for that.

gcc/ChangeLog:

	* config.gcc (riscv*-*-*): Add support for --with-cmodel configure option.
	(all_defaults): Add cmodel.
	* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Remove.
	* doc/install.texi: Document --with-cmodel configure option.
	* doc/invoke.texi (-mcmodel): Mention --with-cmodel configure option.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
This commit is contained in:
Hau Hsu 2024-08-02 13:11:51 +08:00 • committed by Kito Cheng
parent ccd6ec2317
commit feea589d78
4 changed files with 29 additions and 6 deletions
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23
gcc/config.gcc
View file

@ -4711,7 +4711,7 @@ case "${target}" in
;;
riscv*-*-*)
supported_defaults="abi arch tune riscv_attribute isa_spec tls"
supported_defaults="abi arch tune riscv_attribute isa_spec tls cmodel"
case "${target}" in
riscv-* | riscv32*) xlen=32 ;;
@ -4867,6 +4867,25 @@ case "${target}" in
exit 1
esac
fi
# Handle --with-cmodel.
# Make sure --with-cmodel is valid. If it was not specified,
# use medlow as the default value.
case "${with_cmodel}" in
"" | medlow)
tm_defines="${tm_defines} TARGET_DEFAULT_CMODEL=CM_MEDLOW"
;;
medany)
tm_defines="${tm_defines} TARGET_DEFAULT_CMODEL=CM_MEDANY"
;;
large)
tm_defines="${tm_defines} TARGET_DEFAULT_CMODEL=CM_LARGE"
;;
*)
echo "invalid option for --with-cmodel: '${with_cmodel}', available values are 'medlow' 'medany' 'large'" 1>&2
exit 1
;;
esac
;;
mips*-*-*)
@ -6046,7 +6065,7 @@ case ${target} in
esac
t=
all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec compact-branches msa"
all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec compact-branches msa cmodel"
for option in $all_defaults
do
eval "val=\$with_"`echo $option | sed s/-/_/g`

2
gcc/config/riscv/riscv.h
View file

@ -119,8 +119,6 @@ ASM_MISA_SPEC
"%{march=*:%:riscv_expand_arch(%*)} " \
"%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
#define TARGET_DEFAULT_CMODEL CM_MEDLOW
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""

4
gcc/doc/install.texi
View file

@ -1537,6 +1537,10 @@ Use big endian by default. Provide a multilib for little endian.
Use little endian by default. Provide a multilib for big endian.
@end table
@item --with-cmodel=@var{cmodel}
Specify what code model to use by default.
Currently only implemented for riscv*-*-*.
@item --enable-threads
Specify that the target
supports threads. This affects the Objective-C compiler and runtime

6
gcc/doc/invoke.texi
View file

@ -31104,8 +31104,10 @@ element-misaligned vector memory access.
@item -mcmodel=medlow
Generate code for the medium-low code model. The program and its statically
defined symbols must lie within a single 2 GiB address range and must lie
between absolute addresses @minus{}2 GiB and +2 GiB. Programs can be
statically or dynamically linked. This is the default code model.
between absolute addresses @minus{}2 GiB and +2 GiB. Programs can be statically
or dynamically linked. This is the default code model unless GCC has been
configured with @option{--with-cmodel=} specifying a different default code
model.
@opindex mcmodel=medany
@item -mcmodel=medany