re PR target/71201 (PowerPC XXPERM instruction fails on ISA 3.0 system.)
[gcc] 2016-05-23 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/71201 * config/rs6000/altivec.md (altivec_vperm_<mode>_internal): Drop ISA 3.0 xxperm fusion alternative. (altivec_vperm_v8hiv16qi): Likewise. (altivec_vperm_<mode>_uns_internal): Likewise. (vperm_v8hiv4si): Likewise. (vperm_v16qiv8hi): Likewise. [gcc/testsuite] 2016-05-23 Michael Meissner <meissner@linux.vnet.ibm.com> Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/p9-permute.c: Run test on big endian as well as little endian. [gcc] 2016-05-23 Michael Meissner <meissner@linux.vnet.ibm.com> Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate vpermr/xxpermr on ISA 3.0. (altivec_expand_vec_perm_le): Likewise. * config/rs6000/altivec.md (UNSPEC_VPERMR): New unspec. (altivec_vpermr_<mode>_internal): Add VPERMR/XXPERMR support for ISA 3.0. Co-Authored-By: Kelvin Nilsen <kelvin@gcc.gnu.org> From-SVN: r236617
This commit is contained in:
Michael Meissner
Michael Meissner
parent
290279c438
commit
fe3f334041
5 changed files with 111 additions and 59 deletions
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@ -1,3 +1,23 @@
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2016-05-23 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/71201
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* config/rs6000/altivec.md (altivec_vperm_<mode>_internal): Drop
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ISA 3.0 xxperm fusion alternative.
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(altivec_vperm_v8hiv16qi): Likewise.
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(altivec_vperm_<mode>_uns_internal): Likewise.
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(vperm_v8hiv4si): Likewise.
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(vperm_v16qiv8hi): Likewise.
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2016-05-23 Michael Meissner <meissner@linux.vnet.ibm.com>
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Kelvin Nilsen <kelvin@gcc.gnu.org>
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* config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate
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vpermr/xxpermr on ISA 3.0.
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(altivec_expand_vec_perm_le): Likewise.
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* config/rs6000/altivec.md (UNSPEC_VPERMR): New unspec.
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(altivec_vpermr_<mode>_internal): Add VPERMR/XXPERMR support for
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ISA 3.0.
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2016-05-23 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (IS_STACK_MODE): Enable for
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@ -58,6 +58,7 @@
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UNSPEC_VSUM2SWS
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UNSPEC_VSUMSWS
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UNSPEC_VPERM
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UNSPEC_VPERMR
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UNSPEC_VPERM_UNS
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UNSPEC_VRFIN
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UNSPEC_VCFUX
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@ -1952,32 +1953,30 @@
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;; Slightly prefer vperm, since the target does not overlap the source
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(define_insn "*altivec_vperm_<mode>_internal"
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[(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo")
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(match_operand:VM 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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[(set (match_operand:VM 0 "register_operand" "=v,?wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0")
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(match_operand:VM 2 "register_operand" "v,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(set_attr "length" "4")])
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(define_insn "altivec_vperm_v8hiv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "=v,?wo,?&wo")
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(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0,wo")
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(match_operand:V8HI 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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[(set (match_operand:V16QI 0 "register_operand" "=v,?wo")
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(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0")
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(match_operand:V8HI 2 "register_operand" "v,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(set_attr "length" "4")])
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(define_expand "altivec_vperm_<mode>_uns"
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[(set (match_operand:VM 0 "register_operand" "")
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@ -1995,18 +1994,17 @@
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})
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(define_insn "*altivec_vperm_<mode>_uns_internal"
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[(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo")
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(match_operand:VM 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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[(set (match_operand:VM 0 "register_operand" "=v,?wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0")
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(match_operand:VM 2 "register_operand" "v,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo")]
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UNSPEC_VPERM_UNS))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(set_attr "length" "4")])
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(define_expand "vec_permv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "")
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@ -2035,6 +2033,19 @@
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FAIL;
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})
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(define_insn "*altivec_vpermr_<mode>_internal"
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[(set (match_operand:VM 0 "register_operand" "=v,?wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0")
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(match_operand:VM 2 "register_operand" "v,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo")]
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UNSPEC_VPERMR))]
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"TARGET_P9_VECTOR"
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"@
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vpermr %0,%1,%2,%3
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xxpermr %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4")])
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(define_insn "altivec_vrfip" ; ceil
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[(set (match_operand:V4SF 0 "register_operand" "=v")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
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@ -2844,32 +2855,30 @@
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"")
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(define_insn "vperm_v8hiv4si"
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[(set (match_operand:V4SI 0 "register_operand" "=v,?wo,?&wo")
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(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0,wo")
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(match_operand:V4SI 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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[(set (match_operand:V4SI 0 "register_operand" "=v,?wo")
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(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0")
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(match_operand:V4SI 2 "register_operand" "v,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo")]
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UNSPEC_VPERMSI))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(set_attr "length" "4")])
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(define_insn "vperm_v16qiv8hi"
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[(set (match_operand:V8HI 0 "register_operand" "=v,?wo,?&wo")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0,wo")
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(match_operand:V8HI 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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[(set (match_operand:V8HI 0 "register_operand" "=v,?wo")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0")
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(match_operand:V8HI 2 "register_operand" "v,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo")]
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UNSPEC_VPERMHI))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(set_attr "length" "4")])
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(define_expand "vec_unpacku_hi_v16qi"
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@ -6863,21 +6863,29 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt)
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gen_rtvec (3, target, reg,
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force_reg (V16QImode, x)),
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UNSPEC_VPERM);
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else
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else
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{
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/* Invert selector. We prefer to generate VNAND on P8 so
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that future fusion opportunities can kick in, but must
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generate VNOR elsewhere. */
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rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
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rtx iorx = (TARGET_P8_VECTOR
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? gen_rtx_IOR (V16QImode, notx, notx)
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: gen_rtx_AND (V16QImode, notx, notx));
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rtx tmp = gen_reg_rtx (V16QImode);
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emit_insn (gen_rtx_SET (tmp, iorx));
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if (TARGET_P9_VECTOR)
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x = gen_rtx_UNSPEC (mode,
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gen_rtvec (3, target, reg,
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force_reg (V16QImode, x)),
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UNSPEC_VPERMR);
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else
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{
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/* Invert selector. We prefer to generate VNAND on P8 so
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that future fusion opportunities can kick in, but must
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generate VNOR elsewhere. */
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rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
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rtx iorx = (TARGET_P8_VECTOR
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? gen_rtx_IOR (V16QImode, notx, notx)
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: gen_rtx_AND (V16QImode, notx, notx));
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rtx tmp = gen_reg_rtx (V16QImode);
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emit_insn (gen_rtx_SET (tmp, iorx));
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/* Permute with operands reversed and adjusted selector. */
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x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
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UNSPEC_VPERM);
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/* Permute with operands reversed and adjusted selector. */
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x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
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UNSPEC_VPERM);
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}
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}
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emit_insn (gen_rtx_SET (target, x));
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@ -34365,17 +34373,25 @@ altivec_expand_vec_perm_le (rtx operands[4])
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if (!REG_P (target))
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tmp = gen_reg_rtx (mode);
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/* Invert the selector with a VNAND if available, else a VNOR.
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The VNAND is preferred for future fusion opportunities. */
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notx = gen_rtx_NOT (V16QImode, sel);
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iorx = (TARGET_P8_VECTOR
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? gen_rtx_IOR (V16QImode, notx, notx)
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: gen_rtx_AND (V16QImode, notx, notx));
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emit_insn (gen_rtx_SET (norreg, iorx));
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if (TARGET_P9_VECTOR)
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{
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unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op0, op1, sel),
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UNSPEC_VPERMR);
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}
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else
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{
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/* Invert the selector with a VNAND if available, else a VNOR.
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The VNAND is preferred for future fusion opportunities. */
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notx = gen_rtx_NOT (V16QImode, sel);
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iorx = (TARGET_P8_VECTOR
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? gen_rtx_IOR (V16QImode, notx, notx)
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: gen_rtx_AND (V16QImode, notx, notx));
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emit_insn (gen_rtx_SET (norreg, iorx));
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/* Permute with operands reversed and adjusted selector. */
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unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
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UNSPEC_VPERM);
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/* Permute with operands reversed and adjusted selector. */
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unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
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UNSPEC_VPERM);
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}
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/* Copy into target, possibly by way of a register. */
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if (!REG_P (target))
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@ -1,3 +1,9 @@
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2016-05-23 Michael Meissner <meissner@linux.vnet.ibm.com>
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Kelvin Nilsen <kelvin@gcc.gnu.org>
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* gcc.target/powerpc/p9-permute.c: Run test on big endian as well
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as little endian.
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2016-05-23 Paolo Carlini <paolo.carlini@oracle.com>
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PR c++/70972
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@ -1,4 +1,4 @@
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/* { dg-do compile { target { powerpc64le-*-* } } } */
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/* { dg-do compile { target { powerpc64*-*-* } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-options "-mcpu=power9 -O2" } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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@ -17,5 +17,6 @@ permute (vector long long *p, vector long long *q, vector unsigned char mask)
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return vec_perm (a, b, mask);
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}
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/* expect xxpermr on little-endian, xxperm on big-endian */
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/* { dg-final { scan-assembler "xxperm" } } */
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/* { dg-final { scan-assembler-not "vperm" } } */
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