i386-c.c (ix86_target_macros_internal): Separate PROCESSOR_COREI7_AVX out from PROCESSOR_COREI7.
2013-11-04 Wei Mi <wmi@google.com>
* gcc/config/i386/i386-c.c (ix86_target_macros_internal): Separate
PROCESSOR_COREI7_AVX out from PROCESSOR_COREI7.
* gcc/config/i386/i386.c (ix86_option_override_internal): Ditto.
(ix86_issue_rate): Ditto.
(ix86_adjust_cost): Ditto.
(ia32_multipass_dfa_lookahead): Ditto.
(ix86_sched_init_global): Ditto.
(get_builtin_code_for_version): Ditto.
* gcc/config/i386/i386.h (enum target_cpu_default): Ditto.
(enum processor_type): Ditto.
* gcc/config/i386/x86-tune.def (DEF_TUNE): Ditto.
From-SVN: r204367
This commit is contained in:
Wei Mi
Wei Mi
parent
8cfa63d223
commit
fd5564d3c7
5 changed files with 41 additions and 5 deletions
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@ -1,3 +1,17 @@
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2013-11-04 Wei Mi <wmi@google.com>
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* gcc/config/i386/i386-c.c (ix86_target_macros_internal): Separate
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PROCESSOR_COREI7_AVX out from PROCESSOR_COREI7.
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* gcc/config/i386/i386.c (ix86_option_override_internal): Ditto.
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(ix86_issue_rate): Ditto.
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(ix86_adjust_cost): Ditto.
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(ia32_multipass_dfa_lookahead): Ditto.
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(ix86_sched_init_global): Ditto.
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(get_builtin_code_for_version): Ditto.
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* gcc/config/i386/i386.h (enum target_cpu_default): Ditto.
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(enum processor_type): Ditto.
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* gcc/config/i386/x86-tune.def (DEF_TUNE): Ditto.
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2013-11-04 Vladimir Makarov <vmakarov@redhat.com>
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PR rtl-optimization/58967
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@ -141,6 +141,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__corei7");
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def_or_undef (parse_in, "__corei7__");
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break;
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case PROCESSOR_COREI7_AVX:
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def_or_undef (parse_in, "__corei7_avx");
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def_or_undef (parse_in, "__corei7_avx__");
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break;
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case PROCESSOR_HASWELL:
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def_or_undef (parse_in, "__core_avx2");
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def_or_undef (parse_in, "__core_avx2__");
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@ -238,6 +242,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_COREI7:
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def_or_undef (parse_in, "__tune_corei7__");
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break;
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case PROCESSOR_COREI7_AVX:
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def_or_undef (parse_in, "__tune_corei7_avx__");
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break;
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case PROCESSOR_HASWELL:
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def_or_undef (parse_in, "__tune_core_avx2__");
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break;
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@ -1833,8 +1833,9 @@ const struct processor_costs *ix86_cost = &pentium_cost;
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#define m_P4_NOCONA (m_PENT4 | m_NOCONA)
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#define m_CORE2 (1<<PROCESSOR_CORE2)
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#define m_COREI7 (1<<PROCESSOR_COREI7)
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#define m_COREI7_AVX (1<<PROCESSOR_COREI7_AVX)
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#define m_HASWELL (1<<PROCESSOR_HASWELL)
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#define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
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#define m_CORE_ALL (m_CORE2 | m_COREI7 | m_COREI7_AVX | m_HASWELL)
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#define m_ATOM (1<<PROCESSOR_ATOM)
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#define m_SLM (1<<PROCESSOR_SLM)
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@ -2299,6 +2300,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
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{&core_cost, 16, 10, 16, 10, 16},
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/* Core i7 */
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{&core_cost, 16, 10, 16, 10, 16},
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/* Core i7 avx */
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{&core_cost, 16, 10, 16, 10, 16},
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/* Core avx2 */
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{&core_cost, 16, 10, 16, 10, 16},
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{&generic_cost, 16, 10, 16, 10, 16},
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@ -2328,6 +2331,7 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
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"nocona",
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"core2",
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"corei7",
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"corei7-avx",
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"core-avx2",
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"atom",
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"slm",
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@ -3016,12 +3020,12 @@ ix86_option_override_internal (bool main_args_p,
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{"corei7", PROCESSOR_COREI7, CPU_COREI7,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
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| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
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{"corei7-avx", PROCESSOR_COREI7, CPU_COREI7,
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{"corei7-avx", PROCESSOR_COREI7_AVX, CPU_COREI7,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
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| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
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| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
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{"core-avx-i", PROCESSOR_COREI7, CPU_COREI7,
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{"core-avx-i", PROCESSOR_COREI7_AVX, CPU_COREI7,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
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| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
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@ -24807,6 +24811,7 @@ ix86_issue_rate (void)
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case PROCESSOR_CORE2:
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case PROCESSOR_COREI7:
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case PROCESSOR_COREI7_AVX:
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case PROCESSOR_HASWELL:
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return 4;
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@ -25103,6 +25108,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
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case PROCESSOR_CORE2:
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case PROCESSOR_COREI7:
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case PROCESSOR_COREI7_AVX:
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case PROCESSOR_HASWELL:
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memory = get_attr_memory (insn);
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@ -25181,6 +25187,7 @@ ia32_multipass_dfa_lookahead (void)
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case PROCESSOR_CORE2:
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case PROCESSOR_COREI7:
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case PROCESSOR_COREI7_AVX:
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case PROCESSOR_HASWELL:
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case PROCESSOR_ATOM:
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case PROCESSOR_SLM:
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@ -25821,6 +25828,7 @@ ix86_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
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{
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case PROCESSOR_CORE2:
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case PROCESSOR_COREI7:
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case PROCESSOR_COREI7_AVX:
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case PROCESSOR_HASWELL:
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/* Do not perform multipass scheduling for pre-reload schedule
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to save compile time. */
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@ -29672,6 +29680,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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arg_str = "corei7";
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priority = P_PROC_SSE4_2;
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break;
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case PROCESSOR_COREI7_AVX:
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arg_str = "corei7-avx";
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priority = P_PROC_SSE4_2;
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break;
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case PROCESSOR_ATOM:
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arg_str = "atom";
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priority = P_PROC_SSSE3;
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@ -304,6 +304,7 @@ extern const struct processor_costs ix86_size_cost;
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#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
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#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
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#define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
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#define TARGET_COREI7_AVX (ix86_tune == PROCESSOR_COREI7_AVX)
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#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
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#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
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#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
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@ -613,6 +614,7 @@ enum target_cpu_default
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TARGET_CPU_DEFAULT_nocona,
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TARGET_CPU_DEFAULT_core2,
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TARGET_CPU_DEFAULT_corei7,
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TARGET_CPU_DEFAULT_corei7_avx,
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TARGET_CPU_DEFAULT_haswell,
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TARGET_CPU_DEFAULT_atom,
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TARGET_CPU_DEFAULT_slm,
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@ -2229,6 +2231,7 @@ enum processor_type
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PROCESSOR_NOCONA,
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PROCESSOR_CORE2,
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PROCESSOR_COREI7,
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PROCESSOR_COREI7_AVX,
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PROCESSOR_HASWELL,
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PROCESSOR_GENERIC,
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PROCESSOR_AMDFAM10,
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@ -300,12 +300,12 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
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/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
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of a sequence loading registers by parts. */
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DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
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m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
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m_COREI7 | m_COREI7_AVX | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
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/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
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of a sequence loading registers by parts. */
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DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
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m_COREI7 | m_BDVER | m_SLM | m_GENERIC)
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m_COREI7 | m_COREI7_AVX | m_BDVER | m_SLM | m_GENERIC)
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/* Use packed single precision instructions where posisble. I.e. movups instead
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of movupd. */
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