Implement permutation with pslldq + psrldq + por when pshufb is not available.
pand/pandn may be used to clear upper/lower bits of the operands, in that case there will be 4-5 instructions for permutation, and it's still better than scalar codes. gcc/ChangeLog: PR target/105354 * config/i386/i386-expand.cc (expand_vec_perm_pslldq_psrldq_por): New function. (ix86_expand_vec_perm_const_1): Try expand_vec_perm_pslldq_psrldq_por for both 3-instruction and 4/5-instruction sequence. gcc/testsuite/ChangeLog: * gcc.target/i386/pr105354-1.c: New test. * gcc.target/i386/pr105354-2.c: New test.
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3 changed files with 347 additions and 0 deletions
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@ -20941,6 +20941,106 @@ expand_vec_perm_vpshufb2_vpermq_even_odd (struct expand_vec_perm_d *d)
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return true;
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}
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/* Implement permutation with pslldq + psrldq + por when pshufb is not
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available. */
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static bool
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expand_vec_perm_pslldq_psrldq_por (struct expand_vec_perm_d *d, bool pandn)
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{
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unsigned i, nelt = d->nelt;
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unsigned start1, end1 = -1;
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machine_mode vmode = d->vmode, imode;
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int start2 = -1;
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bool clear_op0, clear_op1;
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unsigned inner_size;
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rtx op0, op1, dop1;
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rtx (*gen_vec_shr) (rtx, rtx, rtx);
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rtx (*gen_vec_shl) (rtx, rtx, rtx);
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/* pshufd can be used for V4SI/V2DI under TARGET_SSE2. */
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if (!TARGET_SSE2 || (vmode != E_V16QImode && vmode != E_V8HImode))
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return false;
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start1 = d->perm[0];
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for (i = 1; i < nelt; i++)
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{
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if (d->perm[i] != d->perm[i-1] + 1)
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{
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if (start2 == -1)
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{
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start2 = d->perm[i];
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end1 = d->perm[i-1];
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}
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else
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return false;
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}
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else if (d->perm[i] >= nelt
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&& start2 == -1)
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{
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start2 = d->perm[i];
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end1 = d->perm[i-1];
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}
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}
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clear_op0 = end1 != nelt - 1;
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clear_op1 = start2 % nelt != 0;
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/* pandn/pand is needed to clear upper/lower bits of op0/op1. */
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if (!pandn && (clear_op0 || clear_op1))
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return false;
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if (d->testing_p)
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return true;
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gen_vec_shr = vmode == E_V16QImode ? gen_vec_shr_v16qi : gen_vec_shr_v8hi;
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gen_vec_shl = vmode == E_V16QImode ? gen_vec_shl_v16qi : gen_vec_shl_v8hi;
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imode = GET_MODE_INNER (vmode);
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inner_size = GET_MODE_BITSIZE (imode);
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op0 = gen_reg_rtx (vmode);
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op1 = gen_reg_rtx (vmode);
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if (start1)
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emit_insn (gen_vec_shr (op0, d->op0, GEN_INT (start1 * inner_size)));
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else
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emit_move_insn (op0, d->op0);
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dop1 = d->op1;
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if (d->one_operand_p)
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dop1 = d->op0;
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int shl_offset = end1 - start1 + 1 - start2 % nelt;
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if (shl_offset)
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emit_insn (gen_vec_shl (op1, dop1, GEN_INT (shl_offset * inner_size)));
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else
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emit_move_insn (op1, dop1);
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/* Clear lower/upper bits for op0/op1. */
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if (clear_op0 || clear_op1)
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{
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rtx vec[16];
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rtx const_vec;
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rtx clear;
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for (i = 0; i != nelt; i++)
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{
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if (i < (end1 - start1 + 1))
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vec[i] = gen_int_mode ((HOST_WIDE_INT_1U << inner_size) - 1, imode);
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else
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vec[i] = CONST0_RTX (imode);
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}
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const_vec = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, vec));
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const_vec = validize_mem (force_const_mem (vmode, const_vec));
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clear = force_reg (vmode, const_vec);
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if (clear_op0)
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emit_move_insn (op0, gen_rtx_AND (vmode, op0, clear));
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if (clear_op1)
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emit_move_insn (op1, gen_rtx_AND (vmode,
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gen_rtx_NOT (vmode, clear),
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op1));
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}
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emit_move_insn (d->target, gen_rtx_IOR (vmode, op0, op1));
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return true;
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}
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/* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
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and extract-odd permutations of two V8QI, V8HI, V16QI, V16HI or V32QI
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operands with two "and" and "pack" or two "shift" and "pack" insns.
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@ -21853,6 +21953,9 @@ ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
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if (expand_vec_perm_pshufb2 (d))
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return true;
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if (expand_vec_perm_pslldq_psrldq_por (d, false))
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return true;
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if (expand_vec_perm_interleave3 (d))
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return true;
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@ -21891,6 +21994,10 @@ ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
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if (expand_vec_perm_even_odd (d))
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return true;
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/* Generate four or five instructions. */
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if (expand_vec_perm_pslldq_psrldq_por (d, true))
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return true;
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/* Even longer sequences. */
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if (expand_vec_perm_vpshufb4_vpermq2 (d))
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return true;
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130
gcc/testsuite/gcc.target/i386/pr105354-1.c
Normal file
130
gcc/testsuite/gcc.target/i386/pr105354-1.c
Normal file
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@ -0,0 +1,130 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -msse2 -mno-ssse3" } */
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/* { dg-final { scan-assembler-times {(?n)psrldq[\t ]+} 16 } } */
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/* { dg-final { scan-assembler-times {(?n)pslldq[\t ]+} 16 } } */
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/* { dg-final { scan-assembler-times {(?n)por[\t ]+} 16 } } */
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/* { dg-final { scan-assembler-times {(?n)pandn[\t ]+} 8 } } */
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/* { dg-final { scan-assembler-times {(?n)pand[\t ]+} 8 } } */
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typedef short v8hi __attribute__((vector_size (16)));
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typedef char v16qi __attribute__((vector_size (16)));
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v16qi
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__attribute__((noipa))
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foo (v16qi a, v16qi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 15, 16, 17, 18, 19, 20);
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}
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v16qi
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__attribute__((noipa))
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foo1 (v16qi a, v16qi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 15, 18, 19, 20, 21, 22);
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}
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v16qi
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__attribute__((noipa))
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foo2 (v16qi a, v16qi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 16, 17, 18, 19, 20, 21);
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}
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v16qi
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__attribute__((noipa))
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foo3 (v16qi a, v16qi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 17, 18, 19, 20, 21, 22);
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}
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v8hi
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__attribute__((noipa))
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foo4 (v8hi a, v8hi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 7, 8, 9, 10, 11, 12);
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}
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v8hi
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__attribute__((noipa))
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foo5 (v8hi a, v8hi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 7, 9, 10, 11, 12, 13);
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}
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v8hi
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__attribute__((noipa))
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foo6 (v8hi a, v8hi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 8, 9, 10, 11, 12, 13);
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}
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v8hi
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__attribute__((noipa))
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foo7 (v8hi a, v8hi b)
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{
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return __builtin_shufflevector (a, b, 5, 6, 9, 10, 11, 12, 13, 14);
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}
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v16qi
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__attribute__((noipa))
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foo8 (v16qi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 15, 16, 17, 18, 19, 20);
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}
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v16qi
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__attribute__((noipa))
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foo9 (v16qi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 15, 18, 19, 20, 21, 22);
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}
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v16qi
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__attribute__((noipa))
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foo10 (v16qi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 16, 17, 18, 19, 20, 21);
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}
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v16qi
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__attribute__((noipa))
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foo11 (v16qi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 17, 18, 19, 20, 21, 22);
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}
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v8hi
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__attribute__((noipa))
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foo12 (v8hi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 7, 8, 9, 10, 11, 12);
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}
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v8hi
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__attribute__((noipa))
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foo13 (v8hi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 7, 9, 10, 11, 12, 13);
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}
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v8hi
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__attribute__((noipa))
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foo14 (v8hi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 8, 9, 10, 11, 12, 13);
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}
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v8hi
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__attribute__((noipa))
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foo15 (v8hi a)
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{
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return __builtin_shufflevector (a, a, 5, 6, 9, 10, 11, 12, 13, 14);
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}
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110
gcc/testsuite/gcc.target/i386/pr105354-2.c
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110
gcc/testsuite/gcc.target/i386/pr105354-2.c
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@ -0,0 +1,110 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -msse2 -mno-ssse3" } */
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/* { dg-require-effective-target sse2 } */
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#include "sse2-check.h"
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#include "pr105354-1.c"
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void
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sse2_test (void)
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{
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union128i_b a, b, res_ab, exp_ab;
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union128i_w c, d, res_cd, exp_cd;
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for (int i = 0; i != 16;i++)
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{
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a.a[i] = i;
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b.a[i] = i + 16;
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res_ab.a[i] = 0;
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exp_ab.a[i] = -1;
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if (i <= 8)
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{
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c.a[i] = i;
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d.a[i] = i + 8;
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res_cd.a[i] = 0;
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exp_cd.a[i] = -1;
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}
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}
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res_ab.x = (__m128i)foo ((v16qi)a.x, (v16qi)b.x);
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 };
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if (check_union128i_b (exp_ab, res_ab.a))
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abort ();
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 18, 19, 20, 21, 22 };
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res_ab.x = (__m128i)foo1 ((v16qi)a.x, (v16qi)b.x);
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if (check_union128i_b (exp_ab, res_ab.a))
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abort();
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21 };
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res_ab.x = (__m128i)foo2 ((v16qi)a.x, (v16qi)b.x);
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if (check_union128i_b (exp_ab, res_ab.a))
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abort();
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 19, 20, 21, 22 };
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res_ab.x = (__m128i)foo3 ((v16qi)a.x, (v16qi)b.x);
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if (check_union128i_b (exp_ab, res_ab.a))
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abort();
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res_ab.x = (__m128i)foo8 ((v16qi)a.x);
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4 };
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if (check_union128i_b (exp_ab, res_ab.a))
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abort ();
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 2, 3, 4, 5, 6 };
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res_ab.x = (__m128i)foo9 ((v16qi)a.x);
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if (check_union128i_b (exp_ab, res_ab.a))
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abort();
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 1, 2, 3, 4, 5 };
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res_ab.x = (__m128i)foo10 ((v16qi)a.x);
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if (check_union128i_b (exp_ab, res_ab.a))
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abort();
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exp_ab.x = __extension__(__m128i) (v16qi) { 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 1, 2, 3, 4, 5, 6 };
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res_ab.x = (__m128i)foo11 ((v16qi)a.x);
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if (check_union128i_b (exp_ab, res_ab.a))
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abort();
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res_cd.x = (__m128i)foo4 ((v8hi)c.x, (v8hi)d.x);
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 7, 8, 9, 10, 11, 12 };
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if (check_union128i_w (exp_cd, res_cd.a))
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abort ();
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 7, 9, 10, 11, 12, 13 };
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res_cd.x = (__m128i)foo5 ((v8hi)c.x, (v8hi)d.x);
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if (check_union128i_w (exp_cd, res_cd.a))
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abort();
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 8, 9, 10, 11, 12, 13 };
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res_cd.x = (__m128i)foo6 ((v8hi)c.x, (v8hi)d.x);
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if (check_union128i_w (exp_cd, res_cd.a))
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abort();
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res_cd.x = (__m128i)foo7 ((v8hi)c.x, (v8hi)d.x);
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 9, 10, 11, 12, 13, 14 };
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if (check_union128i_w (exp_cd, res_cd.a))
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abort ();
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 7, 0, 1, 2, 3, 4 };
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res_cd.x = (__m128i)foo12 ((v8hi)c.x);
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if (check_union128i_w (exp_cd, res_cd.a))
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abort();
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 7, 1, 2, 3, 4, 5 };
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res_cd.x = (__m128i)foo13 ((v8hi)c.x);
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if (check_union128i_w (exp_cd, res_cd.a))
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abort();
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 0, 1, 2, 3, 4, 5 };
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res_cd.x = (__m128i)foo14 ((v8hi)c.x);
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if (check_union128i_w (exp_cd, res_cd.a))
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abort();
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exp_cd.x = __extension__(__m128i) (v8hi) { 5, 6, 1, 2, 3, 4, 5, 6 };
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res_cd.x = (__m128i)foo15 ((v8hi)c.x);
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if (check_union128i_w (exp_cd, res_cd.a))
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abort();
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}
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