rs6000: Fix vec insert ilp32 ICE and test failures [PR98799]
UNSPEC_SI_FROM_SF is not supported when TARGET_DIRECT_MOVE_64BIT
is false for -m32, don't generate VIEW_CONVERT_EXPR(ARRAY_REF) for
variable vector insert. Remove rs6000_expand_vector_set_var helper
function, adjust the p8 and p9 definitions position and make them
static.
The previous commit r11-6858 missed check m32, This patch is tested pass
on P7BE{m32,m64}/P8BE{m32,m64}/P8LE/P9LE with
RUNTESTFLAGS="--target_board =unix'{-m32,-m64}'" for BE targets.
gcc/ChangeLog:
2021-01-27 Xionghu Luo <luoxhu@linux.ibm.com>
David Edelsohn <dje.gcc@gmail.com>
PR target/98799
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Don't generate VIEW_CONVERT_EXPR for fcode ALTIVEC_BUILTIN_VEC_INSERT
when -m32.
* config/rs6000/rs6000-protos.h (rs6000_expand_vector_set_var):
Delete.
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Remove the
wrapper call rs6000_expand_vector_set_var for cleanup. Call
rs6000_expand_vector_set_var_p9 and rs6000_expand_vector_set_var_p8
directly.
(rs6000_expand_vector_set_var): Delete.
(rs6000_expand_vector_set_var_p9): Make static.
(rs6000_expand_vector_set_var_p8): Make static.
gcc/testsuite/ChangeLog:
2021-01-27 Xionghu Luo <luoxhu@linux.ibm.com>
PR target/98827
* gcc.target/powerpc/fold-vec-insert-char-p8.c: Adjust ilp32.
* gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-double.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise.
* gcc.target/powerpc/pr79251.p8.c: Likewise.
* gcc.target/powerpc/pr79251.p9.c: Likewise.
* gcc.target/powerpc/vsx-builtin-7.c: Likewise.
* gcc.target/powerpc/pr79251-run.c: Build and run with vsx
option.
This commit is contained in:
Xionghu Luo
parent
f76d0d8645
commit
fbe37371cf
17 changed files with 208 additions and 175 deletions
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@ -1600,7 +1600,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
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stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
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}
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if (TARGET_P8_VECTOR)
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if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
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{
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stmt = build_array_ref (loc, stmt, arg2);
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stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt,
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@ -58,7 +58,6 @@ extern bool rs6000_split_128bit_ok_p (rtx []);
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extern void rs6000_expand_float128_convert (rtx, rtx, bool);
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extern void rs6000_expand_vector_init (rtx, rtx);
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extern void rs6000_expand_vector_set (rtx, rtx, rtx);
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extern void rs6000_expand_vector_set_var (rtx, rtx, rtx);
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extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
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extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
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extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode);
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@ -6984,122 +6984,10 @@ rs6000_expand_vector_init (rtx target, rtx vals)
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emit_move_insn (target, mem);
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}
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/* Set field ELT_RTX of TARGET to VAL. */
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void
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rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
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{
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machine_mode mode = GET_MODE (target);
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machine_mode inner_mode = GET_MODE_INNER (mode);
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rtx reg = gen_reg_rtx (mode);
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rtx mask, mem, x;
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int width = GET_MODE_SIZE (inner_mode);
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int i;
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val = force_reg (GET_MODE (val), val);
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if (VECTOR_MEM_VSX_P (mode))
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{
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if (!CONST_INT_P (elt_rtx))
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{
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rs6000_expand_vector_set_var (target, val, elt_rtx);
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return;
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}
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rtx insn = NULL_RTX;
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if (mode == V2DFmode)
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insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
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else if (mode == V2DImode)
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insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
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else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
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{
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if (mode == V4SImode)
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insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
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else if (mode == V8HImode)
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insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
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else if (mode == V16QImode)
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insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
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else if (mode == V4SFmode)
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insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
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}
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if (insn)
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{
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emit_insn (insn);
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return;
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}
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}
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gcc_assert (CONST_INT_P (elt_rtx));
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/* Simplify setting single element vectors like V1TImode. */
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if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode)
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&& INTVAL (elt_rtx) == 0)
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{
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emit_move_insn (target, gen_lowpart (mode, val));
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return;
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}
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/* Load single variable value. */
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mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
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emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
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x = gen_rtx_UNSPEC (VOIDmode,
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gen_rtvec (1, const0_rtx), UNSPEC_LVE);
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emit_insn (gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (2,
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gen_rtx_SET (reg, mem),
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x)));
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/* Linear sequence. */
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mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
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for (i = 0; i < 16; ++i)
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XVECEXP (mask, 0, i) = GEN_INT (i);
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/* Set permute mask to insert element into target. */
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for (i = 0; i < width; ++i)
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XVECEXP (mask, 0, INTVAL (elt_rtx) * width + i) = GEN_INT (i + 0x10);
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x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
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if (BYTES_BIG_ENDIAN)
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x = gen_rtx_UNSPEC (mode,
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gen_rtvec (3, target, reg,
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force_reg (V16QImode, x)),
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UNSPEC_VPERM);
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else
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{
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if (TARGET_P9_VECTOR)
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x = gen_rtx_UNSPEC (mode,
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gen_rtvec (3, reg, target,
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force_reg (V16QImode, x)),
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UNSPEC_VPERMR);
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else
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{
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/* Invert selector. We prefer to generate VNAND on P8 so
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that future fusion opportunities can kick in, but must
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generate VNOR elsewhere. */
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rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
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rtx iorx = (TARGET_P8_VECTOR
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? gen_rtx_IOR (V16QImode, notx, notx)
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: gen_rtx_AND (V16QImode, notx, notx));
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rtx tmp = gen_reg_rtx (V16QImode);
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emit_insn (gen_rtx_SET (tmp, iorx));
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/* Permute with operands reversed and adjusted selector. */
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x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
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UNSPEC_VPERM);
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}
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}
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emit_insn (gen_rtx_SET (target, x));
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}
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/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX
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is variable and also counts by vector element size for p9 and above. */
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void
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static void
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rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
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{
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machine_mode mode = GET_MODE (target);
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@ -7146,7 +7034,7 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
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/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX
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is variable and also counts by vector element size for p8. */
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void
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static void
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rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
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{
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machine_mode mode = GET_MODE (target);
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@ -7242,18 +7130,126 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
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gen_vector_select_v16qi (target_v16qi, target_v16qi, val_perm, mask_perm));
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}
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/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX
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is variable and also counts by vector element size. */
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/* Set field ELT_RTX of TARGET to VAL. */
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void
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rs6000_expand_vector_set_var (rtx target, rtx val, rtx idx)
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rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
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{
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machine_mode mode = GET_MODE (target);
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machine_mode inner_mode = GET_MODE_INNER (mode);
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if (TARGET_P9_VECTOR || GET_MODE_SIZE (inner_mode) == 8)
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rs6000_expand_vector_set_var_p9 (target, val, idx);
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rtx reg = gen_reg_rtx (mode);
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rtx mask, mem, x;
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int width = GET_MODE_SIZE (inner_mode);
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int i;
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val = force_reg (GET_MODE (val), val);
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if (VECTOR_MEM_VSX_P (mode))
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{
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if (!CONST_INT_P (elt_rtx))
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{
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/* For V2DI/V2DF, could leverage the P9 version to generate xxpermdi
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when elt_rtx is variable. */
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if ((TARGET_P9_VECTOR && TARGET_POWERPC64) || width == 8)
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{
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rs6000_expand_vector_set_var_p9 (target, val, elt_rtx);
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return;
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}
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else if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
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{
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rs6000_expand_vector_set_var_p8 (target, val, elt_rtx);
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return;
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}
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}
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rtx insn = NULL_RTX;
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if (mode == V2DFmode)
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insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
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else if (mode == V2DImode)
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insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
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else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
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{
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if (mode == V4SImode)
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insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
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else if (mode == V8HImode)
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insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
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else if (mode == V16QImode)
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insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
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else if (mode == V4SFmode)
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insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
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}
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if (insn)
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{
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emit_insn (insn);
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return;
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}
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}
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gcc_assert (CONST_INT_P (elt_rtx));
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/* Simplify setting single element vectors like V1TImode. */
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if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode)
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&& INTVAL (elt_rtx) == 0)
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{
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emit_move_insn (target, gen_lowpart (mode, val));
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return;
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}
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/* Load single variable value. */
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mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
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emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
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x = gen_rtx_UNSPEC (VOIDmode,
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gen_rtvec (1, const0_rtx), UNSPEC_LVE);
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emit_insn (gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (2,
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gen_rtx_SET (reg, mem),
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x)));
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/* Linear sequence. */
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mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
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for (i = 0; i < 16; ++i)
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XVECEXP (mask, 0, i) = GEN_INT (i);
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/* Set permute mask to insert element into target. */
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for (i = 0; i < width; ++i)
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XVECEXP (mask, 0, INTVAL (elt_rtx) * width + i) = GEN_INT (i + 0x10);
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x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
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if (BYTES_BIG_ENDIAN)
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x = gen_rtx_UNSPEC (mode,
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gen_rtvec (3, target, reg,
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force_reg (V16QImode, x)),
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UNSPEC_VPERM);
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else
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rs6000_expand_vector_set_var_p8 (target, val, idx);
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{
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if (TARGET_P9_VECTOR)
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x = gen_rtx_UNSPEC (mode,
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gen_rtvec (3, reg, target,
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force_reg (V16QImode, x)),
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UNSPEC_VPERMR);
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else
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{
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/* Invert selector. We prefer to generate VNAND on P8 so
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that future fusion opportunities can kick in, but must
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generate VNOR elsewhere. */
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rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
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rtx iorx = (TARGET_P8_VECTOR
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? gen_rtx_IOR (V16QImode, notx, notx)
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: gen_rtx_AND (V16QImode, notx, notx));
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rtx tmp = gen_reg_rtx (V16QImode);
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emit_insn (gen_rtx_SET (tmp, iorx));
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/* Permute with operands reversed and adjusted selector. */
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x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
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UNSPEC_VPERM);
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}
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}
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emit_insn (gen_rtx_SET (target, x));
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}
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/* Extract field ELT from VEC into TARGET. */
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@ -45,15 +45,21 @@ vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
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}
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/* no store per _var test */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 0 } } */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 0 { target lp64 } } } */
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/* one store-byte per test */
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/* { dg-final { scan-assembler-times {\mstb\M} 4 } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 4 { target lp64 } } } */
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/* one load per test */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target le } } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target be } } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && lp64 } } } } */
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/* one lvebx per _cst test.*/
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/* { dg-final { scan-assembler-times {\mlvebx\M} 4 } } */
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/* one vperm per _cst test.*/
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/* { dg-final { scan-assembler-times {\mvperm\M} 12 } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
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/* -m32 codegen. */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
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@ -56,6 +56,6 @@ vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
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/* { dg-final { scan-assembler-times {\mrlwinm\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvebx\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvebx\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
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@ -28,7 +28,11 @@ testd_cst (double d, vector double vd)
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr8 } } } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -19,12 +19,18 @@ testf_cst (float f, vector float vf)
|
|||
return vec_insert (f, vf, 12);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 0 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 0 { target lp64 } } } */
|
||||
/* cst tests has stfs instead of stfsx. */
|
||||
/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 1 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M|\mlxvw4x\M} 2 } } */
|
||||
|
||||
/* cst test has a lvewx,vperm combo */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 3 { target lp64 } } } */
|
||||
|
||||
/* -m32 codegen. */
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,6 @@ testf_cst (float f, vector float vf)
|
|||
|
||||
/* { dg-final { scan-assembler-times {\mstfs\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
|
||||
|
|
|
|||
|
|
@ -50,9 +50,14 @@ testui2_cst(unsigned int x, vector unsigned int v)
|
|||
|
||||
/* Each test has lvx (8). cst tests have additional lvewx. (4) */
|
||||
/* var tests have no stwx and stvx. cst tests have stw (4).*/
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && lp64 } } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ testui2_cst(unsigned int x, vector unsigned int v)
|
|||
}
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstwx\M} 0 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 0 { target lp64 } } } */
|
||||
|
||||
|
|
@ -57,8 +57,9 @@ testui2_cst(unsigned int x, vector unsigned int v)
|
|||
/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 8 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxinsertw\M} 8 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstw\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
|
||||
|
|
|
|||
|
|
@ -60,9 +60,11 @@ testul2_cst(unsigned long long x, vector unsigned long long v)
|
|||
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 4 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 0 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 0 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstdx\M} 0 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 8 { target ilp32 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 4 { target ilp32 } } } */
|
||||
|
|
|
|||
|
|
@ -49,10 +49,14 @@ testus2_cst(unsigned short x, vector unsigned short v)
|
|||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 4 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 4 { target { be && lp64 } } } } */
|
||||
/* stores.. 0 per variable tests, 1 each per cst test. */
|
||||
/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 4 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -51,13 +51,14 @@ testus2_cst(unsigned short x, vector unsigned short v)
|
|||
/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 8 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvinserth\M} 8 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 0 { target lp64 }} } */
|
||||
|
||||
/* -m32 uses sth/lvehx as part of the sequence. */
|
||||
/* { dg-final { scan-assembler-times {\msth\M} 8 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 8 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 8 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\msth\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 } } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
/* { dg-options "-O2 -maltivec" } */
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target vsx_hw } */
|
||||
/* { dg-options "-O2 -mvsx" } */
|
||||
|
||||
#include <stddef.h>
|
||||
#include <altivec.h>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */
|
||||
|
||||
#include <stddef.h>
|
||||
#include <altivec.h>
|
||||
|
|
@ -9,9 +9,16 @@
|
|||
TEST_VEC_INSERT_ALL (test)
|
||||
|
||||
/* { dg-final { scan-assembler-not {\mstxw\M} } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsl\M} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsr\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 20 } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxsel\M} 7 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsl\M} 10 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsr\M} 3 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 20 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 10 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxsel\M} 7 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb|sth|stw|stfs|stfd\M} 22 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvw4x\M} 6 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M} 4 { target ilp32 } } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_p9vector_ok } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=power9 -maltivec" } */
|
||||
/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */
|
||||
|
||||
#include <stddef.h>
|
||||
#include <altivec.h>
|
||||
|
|
@ -9,16 +9,16 @@
|
|||
TEST_VEC_INSERT_ALL (test)
|
||||
|
||||
/* { dg-final { scan-assembler-not {\mstxw\M} } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsl\M} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsr\M} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 20 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsl\M} 10 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvsr\M} 10 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxperm\M} 20 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxinsertw\M} 3 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvinserth\M} 2 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvinsertb\M} 2 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 7 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvebx\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 2 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 3 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M} 10 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb|sth|stw|stfs|stfd\M} 22 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 10 { target ilp32 } } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ vector unsigned __int128 splat_uint128 (unsigned __int128 x) { return vec_splats
|
|||
/* { dg-final { scan-assembler-times {\mrldic\M} 0 { target { be && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target { be && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 11 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 4 { target be } } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi" 6 { target le } } } */
|
||||
/* { dg-final { scan-assembler-times "vspltisb" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vspltish" 2 } } */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue