rs6000: Delete -mmfpgpr
This patch makes the -mmfpgpr option not do anything except warn that the option is deprecated. * config/rs6000/rs6000.h (MASK_MFPGPR): Delete. * config/rs6000/rs6000.c (direct_move_p): Adjust. (rs6000_secondary_reload_simple_move): Adjust. (rs6000_opt_masks): Neuter the "mfpgpr" option. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Adjust. * config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Adjust comment. (power6x): Adjust. * config/rs6000/rs6000.md (floatsi<mode>2_lfiwax): Adjust. (floatunssi<mode>2_lfiwzx): Adjust. (fix_trunc<mode>si2_stfiwx): Adjust. (fixuns_trunc<mode>si2_stfiwx): Adjust. * config/rs6000/rs6000.opt (mno-mfpgpr): New. (mfpgpr): Mark as deprecated. * doc/extend.texi (PowerPC Function Attributes): Delete mfpgpr. (Basic PowerPC Built-in Functions Available on ISA 2.05): Adjust. * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mmfpgpr. gcc/testsuite/ * gcc.target/powerpc/mmfpgpr.c: Delete. From-SVN: r271889
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
ec7fd7807d
commit
fbd4b7f39e
11 changed files with 48 additions and 79 deletions
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@ -1,3 +1,23 @@
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2019-06-03 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.h (MASK_MFPGPR): Delete.
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* config/rs6000/rs6000.c (direct_move_p): Adjust.
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(rs6000_secondary_reload_simple_move): Adjust.
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(rs6000_opt_masks): Neuter the "mfpgpr" option.
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* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Adjust.
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* config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Adjust
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comment.
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(power6x): Adjust.
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* config/rs6000/rs6000.md (floatsi<mode>2_lfiwax): Adjust.
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(floatunssi<mode>2_lfiwzx): Adjust.
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(fix_trunc<mode>si2_stfiwx): Adjust.
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(fixuns_trunc<mode>si2_stfiwx): Adjust.
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* config/rs6000/rs6000.opt (mno-mfpgpr): New.
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(mfpgpr): Mark as deprecated.
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* doc/extend.texi (PowerPC Function Attributes): Delete mfpgpr.
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(Basic PowerPC Built-in Functions Available on ISA 2.05): Adjust.
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* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mmfpgpr.
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2019-06-03 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/constraints.md (define_register_constraint "wg"):
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@ -430,8 +430,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
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rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
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if ((flags & OPTION_MASK_CMPB) != 0)
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rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
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if ((flags & OPTION_MASK_MFPGPR) != 0)
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rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
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if ((flags & OPTION_MASK_POPCNTD) != 0)
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rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
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/* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
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@ -24,10 +24,9 @@
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#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
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#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
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/* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
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ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
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fre, fsqrt, etc. were no longer documented as optional. Group masks by
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server and embedded. */
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/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
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power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
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as optional. Group masks by server and embedded. */
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#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
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| OPTION_MASK_CMPB \
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| OPTION_MASK_RECIP_PRECISION \
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@ -130,7 +129,6 @@
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| OPTION_MASK_HTM \
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| OPTION_MASK_ISEL \
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| OPTION_MASK_MFCRF \
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| OPTION_MASK_MFPGPR \
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| OPTION_MASK_MODULO \
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| OPTION_MASK_MULHW \
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| OPTION_MASK_NO_UPDATE \
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@ -236,7 +234,7 @@ RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
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| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
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RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
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| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
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| MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
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| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
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RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
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RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
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RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
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@ -7473,30 +7473,22 @@ gpr_or_gpr_p (rtx op0, rtx op1)
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bool
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direct_move_p (rtx op0, rtx op1)
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{
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int regno0, regno1;
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if (!REG_P (op0) || !REG_P (op1))
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return false;
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if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
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if (!TARGET_DIRECT_MOVE)
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return false;
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regno0 = REGNO (op0);
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regno1 = REGNO (op1);
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int regno0 = REGNO (op0);
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int regno1 = REGNO (op1);
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if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
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return false;
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if (INT_REGNO_P (regno0))
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return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
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if (INT_REGNO_P (regno0) && VSX_REGNO_P (regno1))
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return true;
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else if (INT_REGNO_P (regno1))
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{
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if (TARGET_MFPGPR && FP_REGNO_P (regno0))
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return true;
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else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
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return true;
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}
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if (VSX_REGNO_P (regno0) && INT_REGNO_P (regno1))
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return true;
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return false;
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}
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@ -19079,12 +19071,6 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
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return true;
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}
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/* Power6+: MFTGPR or MFFGPR. */
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else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
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&& ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
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|| (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
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return true;
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/* Move to/from SPR. */
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else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
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&& ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
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@ -36452,7 +36438,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
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{ "htm", OPTION_MASK_HTM, false, true },
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{ "isel", OPTION_MASK_ISEL, false, true },
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{ "mfcrf", OPTION_MASK_MFCRF, false, true },
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{ "mfpgpr", OPTION_MASK_MFPGPR, false, true },
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{ "mfpgpr", 0, false, true },
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{ "modulo", OPTION_MASK_MODULO, false, true },
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{ "mulhw", OPTION_MASK_MULHW, false, true },
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{ "multiple", OPTION_MASK_MULTIPLE, false, true },
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@ -509,7 +509,6 @@ extern int rs6000_vector_align[];
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#define MASK_HTM OPTION_MASK_HTM
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#define MASK_ISEL OPTION_MASK_ISEL
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#define MASK_MFCRF OPTION_MASK_MFCRF
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#define MASK_MFPGPR OPTION_MASK_MFPGPR
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#define MASK_MULHW OPTION_MASK_MULHW
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#define MASK_MULTIPLE OPTION_MASK_MULTIPLE
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#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
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@ -5265,8 +5265,7 @@
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rtx src = operands[1];
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rtx tmp;
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if (!MEM_P (src) && TARGET_POWERPC64
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&& (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
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if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
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tmp = convert_to_mode (DImode, src, false);
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else
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{
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@ -5341,8 +5340,7 @@
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rtx src = operands[1];
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rtx tmp;
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if (!MEM_P (src) && TARGET_POWERPC64
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&& (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
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if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
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tmp = convert_to_mode (DImode, src, true);
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else
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{
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@ -5703,7 +5701,7 @@
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emit_insn (gen_stfiwx (dest, tmp));
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DONE;
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}
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else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE) && !MEM_P (dest))
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else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE && !MEM_P (dest))
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{
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dest = gen_lowpart (DImode, dest);
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emit_move_insn (dest, tmp);
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@ -5851,7 +5849,7 @@
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emit_insn (gen_stfiwx (dest, tmp));
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DONE;
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}
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else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
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else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
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{
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dest = gen_lowpart (DImode, dest);
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emit_move_insn (dest, tmp);
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@ -144,9 +144,12 @@ mcmpb
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Target Report Mask(CMPB) Var(rs6000_isa_flags)
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Use PowerPC V2.05 compare bytes instruction.
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;; This option existed in the past, but now is always off.
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mno-mfpgpr
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Target RejectNegative Undocumented Ignore
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mmfpgpr
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Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
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Use extended PowerPC V2.05 move floating point to/from GPR instructions.
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Target RejectNegative Undocumented Deprecated
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maltivec
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Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
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@ -5432,13 +5432,6 @@ Generate code that uses (does not use) the move from condition
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register field instruction implemented on the POWER4 processor and
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other processors that support the PowerPC V2.01 architecture.
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@item mfpgpr
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@itemx no-mfpgpr
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@cindex @code{target("mfpgpr")} function attribute, PowerPC
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Generate code that uses (does not use) the FP move to/from general
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purpose register instructions implemented on the POWER6X processor and
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other processors that support the extended PowerPC V2.05 architecture.
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@item mulhw
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@itemx no-mulhw
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@cindex @code{target("mulhw")} function attribute, PowerPC
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@ -16879,8 +16872,8 @@ enabling the @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
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@option{-mpowerpc-gfxopt}, @option{-mmfcrf}, @option{-mpopcntb},
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@option{-mfprnd}, @option{-mcmpb}, @option{-mhard-dfp}, and
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@option{-mrecip-precision} options. Specify the
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@option{-maltivec} and @option{-mfpgpr} options explicitly in
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combination with the above options if they are desired.
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@option{-maltivec} option explicitly in
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combination with the above options if desired.
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The following functions require option @option{-mcmpb}.
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@smallexample
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@ -1076,7 +1076,7 @@ See RS/6000 and PowerPC Options.
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-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
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-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol
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-mfprnd -mno-fprnd @gol
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-mcmpb -mno-cmpb -mmfpgpr -mno-mfpgpr -mhard-dfp -mno-hard-dfp @gol
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-mcmpb -mno-cmpb -mhard-dfp -mno-hard-dfp @gol
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-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
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-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
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-malign-power -malign-natural @gol
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@ -24014,8 +24014,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
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@need 800
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@itemx -mcmpb
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@itemx -mno-cmpb
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@itemx -mmfpgpr
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@itemx -mno-mfpgpr
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@itemx -mhard-dfp
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@itemx -mno-hard-dfp
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@opindex mpowerpc-gpopt
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@ -24034,8 +24032,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
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@opindex mno-fprnd
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@opindex mcmpb
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@opindex mno-cmpb
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@opindex mmfpgpr
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@opindex mno-mfpgpr
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@opindex mhard-dfp
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@opindex mno-hard-dfp
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You use these options to specify which instructions are available on the
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@ -24069,10 +24065,6 @@ processors that support the PowerPC V2.03 architecture.
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The @option{-mcmpb} option allows GCC to generate the compare bytes
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instruction implemented on the POWER6 processor and other processors
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that support the PowerPC V2.05 architecture.
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The @option{-mmfpgpr} option allows GCC to generate the FP move to/from
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general-purpose register instructions implemented on the POWER6X
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processor and other processors that support the extended PowerPC V2.05
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architecture.
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The @option{-mhard-dfp} option allows GCC to generate the decimal
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floating-point instructions implemented on some POWER processors.
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@ -1,3 +1,7 @@
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2019-06-03 Segher Boessenkool <segher@kernel.crashing.org>
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* gcc.target/powerpc/mmfpgpr.c: Delete.
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2019-06-03 David Edelsohn <dje.gcc@gmail.com>
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* gcc.dg/debug/enum-1.c: Add -fno-eliminate-unused-debug-symbols
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@ -1,22 +0,0 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-O2 -mdejagnu-cpu=power6x -mmfpgpr" } */
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/* { dg-final { scan-assembler "mffgpr" } } */
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/* { dg-final { scan-assembler "mftgpr" } } */
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/* Test that we generate the instructions to move between the GPR and FPR
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registers under power6x. */
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extern long return_long (void);
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extern double return_double (void);
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double return_double2 (void)
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{
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return (double) return_long ();
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}
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long return_long2 (void)
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{
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return (long) return_double ();
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}
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