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iris.h (CTORS_SECTION_ASM_OP,DTORS_SECTION_ASM_OP, [...]): Use Pmode == DImode rather than TARGET_LONG64.

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* config/mips/iris.h (CTORS_SECTION_ASM_OP,DTORS_SECTION_ASM_OP,
	dtors_section): Use Pmode == DImode rather than TARGET_LONG64.
	* config/mips/mips.c (override_options): Allow -mlong64 and
	-mint64 with -mips2 or less.
	* config/mips/mips.h (MASK_LONG64): Fix comment.
	(POINTER_SIZE): Use Pmode == DImode rather than TARGET_LONG64.
	(Pmode): Make Pmode the smaller of longs or gp registers.
	* invoke.texi: Note the new size for pointers.

From-SVN: r25798
This commit is contained in:
Gavin Romig-Koch 1999-03-16 07:25:31 +00:00 • committed by Gavin Romig-Koch
parent 642f15d187
commit fb1bf66d61
5 changed files with 28 additions and 20 deletions
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11
gcc/ChangeLog
View file

@ -1,3 +1,14 @@
Tue Mar 16 10:22:22 1999 Gavin Romig-Koch <gavin@cygnus.com>
* config/mips/iris.h (CTORS_SECTION_ASM_OP,DTORS_SECTION_ASM_OP,
dtors_section): Use Pmode == DImode rather than TARGET_LONG64.
* config/mips/mips.c (override_options): Allow -mlong64 and
-mint64 with -mips2 or less.
* config/mips/mips.h (MASK_LONG64): Fix comment.
(POINTER_SIZE): Use Pmode == DImode rather than TARGET_LONG64.
(Pmode): Make Pmode the smaller of longs or gp registers.
* invoke.texi: Note the new size for pointers.
Mon Mar 15 22:45:25 1999 David Edelsohn <edelsohn@mhpcc.edu>
* rs6000.h (ASM_OUTPUT_{DOUBLE,FLOAT}): Always generate IEEE 754

8
gcc/config/mips/iris6.h
View file

@ -263,9 +263,9 @@ Boston, MA 02111-1307, USA. */
/* If we are included from varasm.c, these need to depend on -mabi. */
#define CTORS_SECTION_ASM_OP \
(TARGET_LONG64 ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
(Pmode == DImode ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
#define DTORS_SECTION_ASM_OP \
(TARGET_LONG64 ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
(Pmode == DImode ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
#endif /* defined (CRT_BEGIN) || defined (CRT_END) */
/* dwarf2out will handle padding this data properly. We definitely don't
@ -341,7 +341,7 @@ dtors_section () \
do { \
ctors_section (); \
fprintf (FILE, "\t%s\t ", \
TARGET_LONG64 ? ".dword" : ".word"); \
(Pmode == DImode) ? ".dword" : ".word"); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)
@ -352,7 +352,7 @@ dtors_section () \
do { \
dtors_section (); \
fprintf (FILE, "\t%s\t ", \
TARGET_LONG64 ? ".dword" : ".word"); \
(Pmode == DImode) ? ".dword" : ".word"); \
assemble_name (FILE, NAME); \
fprintf (FILE, "\n"); \
} while (0)

8
gcc/config/mips/mips.c
View file

@ -4274,13 +4274,7 @@ override_options ()
/* make sure sizes of ints/longs/etc. are ok */
if (mips_isa < 3)
{
if (TARGET_INT64)
fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
else if (TARGET_LONG64)
fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
else if (TARGET_FLOAT64)
if (TARGET_FLOAT64)
fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
else if (TARGET_64BIT)

10
gcc/config/mips/mips.h
View file

@ -315,7 +315,7 @@ extern void mips_select_section ();
/* Bits for real switches */
#define MASK_INT64 0x00000001 /* ints are 64 bits */
#define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
#define MASK_LONG64 0x00000002 /* longs are 64 bits */
#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
@ -1344,7 +1344,7 @@ do { \
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#ifndef POINTER_SIZE
#define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
#define POINTER_SIZE (Pmode == DImode ? 64 : 32)
#endif
/* Allocation boundary (in *bits*) for storing pointers in memory. */
@ -3240,10 +3240,12 @@ while (0)
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
between pointers and any other objects of this machine mode.
For MIPS we make pointers are the smaller of longs and gp-registers. */
#ifndef Pmode
#define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
#define Pmode ((enum machine_mode)((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode))
#endif
/* A function address in a call instruction

11
gcc/invoke.texi
View file

@ -4766,7 +4766,6 @@ ISA level.
@item -mips3
Issue instructions from level 3 of the MIPS ISA (64 bit instructions).
@samp{r4000} is the default @var{cpu type} at this ISA level.
This option does not change the sizes of any of the C data types.
@item -mips4
Issue instructions from level 4 of the MIPS ISA. @samp{r8000} is the
@ -4789,12 +4788,14 @@ Assume that 32 64-bit general purpose registers are available. This is
the default when the @samp{-mips3} option is used.
@item -mint64
Types long, int, and pointer are 64 bits. This works only if @samp{-mips3}
is also specified.
Force int and long types to be 64 bits wide. See @samp{-mlong64} for an
explanation of the width of pointers.
@item -mlong64
Types long and pointer are 64 bits, and type int is 32 bits.
This works only if @samp{-mips3} is also specified.
Force long types to be 64 bits wide.
The width of pointer types is the smaller of the width of longs
or the width of general purpose registers.
@itemx -mabi=32
@itemx -mabi=n32