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re PR target/80425 (Extra inter-unit register move with zero-extension)

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PR target/80425
	* config/i386.i386.md (*zero_extendsidi2): Change (?r,*Yj), (?*Yi,r)
	and (*x,m) to ($r,Yj), ($Yi,r) and ($x,m).
	(zero-extendsidi peephole2): Remove peephole.

testsuite/ChangeLog:

	PR target/80425
	* gcc.target/i386/pr80425-3.c: New test.

From-SVN: r254505
This commit is contained in:
Uros Bizjak 2017-11-07 19:51:22 +01:00
parent 8b36a25018
commit fa97b067e1
4 changed files with 32 additions and 17 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,10 @@
2017-11-07 Uros Bizjak <ubizjak@gmail.com>
PR target/80425
* config/i386.i386.md (*zero_extendsidi2): Change (?r,*Yj), (?*Yi,r)
and (*x,m) to ($r,Yj), ($Yi,r) and ($x,m).
(zero-extendsidi peephole2): Remove peephole.
2017-11-07 Eric Botcazou <ebotcazou@adacore.com>
PR c/53037
@ -7,15 +14,13 @@
2017-11-07 Andrew Waterman <andrew@sifive.com>
* config/riscv/riscv-protos.h (riscv_hard_regno_nregs): New
prototype.
* config/riscv/riscv-protos.h (riscv_hard_regno_nregs): New prototype.
(riscv_expand_block_move): Likewise.
gcc/config/riscv/riscv.h (MOVE_RATIO): Tune cost to movmemsi
* config/riscv/riscv.h (MOVE_RATIO): Tune cost to movmemsi
implementation.
(RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER): New define.
(RISCV_MAX_MOVE_BYTES_STRAIGHT): New define.
gcc/config/riscv/riscv.c (riscv_block_move_straight): New
function.
* config/riscv/riscv.c (riscv_block_move_straight): New function.
(riscv_adjust_block_mem): Likewise.
(riscv_block_move_loop): Likewise.
(riscv_expand_block_move): Likewise.

13
gcc/config/i386/i386.md
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@ -3864,10 +3864,10 @@
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?*Yi,*x,*x,*v,*r")
"=r,?r,?o,r ,o,?*Ym,?!*y,$r,$Yi,$x,*x,*v,*r")
(zero_extend:DI
(match_operand:SI 1 "x86_64_zext_operand"
"0 ,rm,r ,rmWz,0,r ,m ,*Yj,r ,m ,*x,*v,*k")))]
"0 ,rm,r ,rmWz,0,r ,m ,Yj,r ,m ,*x,*v,*k")))]
""
{
switch (get_attr_type (insn))
@ -3983,15 +3983,6 @@
(set (match_dup 4) (const_int 0))]
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
(define_peephole2
[(set (match_operand:DI 0 "general_reg_operand")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand")))
(set (match_operand:DI 2 "sse_reg_operand") (match_dup 0))]
"TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2)
(zero_extend:DI (match_dup 1)))])
(define_mode_attr kmov_isa
[(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")])

7
gcc/testsuite/ChangeLog
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@ -1,8 +1,13 @@
2017-11-07 Uros Bizjak <ubizjak@gmail.com>
PR target/80425
* gcc.target/i386/pr80425-3.c: New test.
2017-11-07 Andreas Schwab <schwab@suse.de>
* g++.dg/pr50763-3.C (evalPoint): Return a value.
2017-10-17 Wilco Dijkstra <wdijkstr@arm.com>
2017-11-07 Wilco Dijkstra <wdijkstr@arm.com>
Jackson Woodruff <jackson.woodruff@arm.com>
PR tree-optimization/71026

14
gcc/testsuite/gcc.target/i386/pr80425-3.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
#include <x86intrin.h>
extern int a;
__m512i
f1 (__m512i x)
{
return _mm512_srai_epi32 (x, a);
}
/* { dg-final { scan-assembler-times "movd\[ \\t\]+\[^\n\]*%xmm" 1 } } */