LoongArch: Add the macro implementation of mcmodel=extreme.
gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p): Add function declaration. * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p): For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend" is not allowed (loongarch_load_tls): Added macro support in extreme mode. (loongarch_call_tls_get_addr): Likewise. (loongarch_legitimize_tls_address): Likewise. (loongarch_force_address): Likewise. (loongarch_legitimize_move): Likewise. (loongarch_output_mi_thunk): Likewise. (loongarch_option_override_internal): Remove the code that detects explicit relocs status. (loongarch_handle_model_attribute): Likewise. * config/loongarch/loongarch.md (movdi_symbolic_off64): New template. * config/loongarch/predicates.md (symbolic_off64_operand): New predicate. (symbolic_off64_or_reg_operand): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/attr-model-5.c: New test. * gcc.target/loongarch/func-call-extreme-5.c: New test. * gcc.target/loongarch/func-call-extreme-6.c: New test. * gcc.target/loongarch/tls-extreme-macro.c: New test.
This commit is contained in:
Lulu Cheng
parent
252f7705a5
commit
fa972949d0
8 changed files with 183 additions and 43 deletions
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@ -222,4 +222,5 @@ extern rtx loongarch_build_signbit_mask (machine_mode, bool, bool);
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extern void loongarch_emit_swrsqrtsf (rtx, rtx, machine_mode, bool);
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extern void loongarch_emit_swdivsf (rtx, rtx, rtx, machine_mode);
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extern bool loongarch_explicit_relocs_p (enum loongarch_symbol_type);
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extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type);
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#endif /* ! GCC_LOONGARCH_PROTOS_H */
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@ -1935,8 +1935,13 @@ loongarch_symbolic_constant_p (rtx x, enum loongarch_symbol_type *symbol_type)
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relocations. */
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switch (*symbol_type)
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{
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case SYMBOL_PCREL:
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case SYMBOL_PCREL64:
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/* When the code model is extreme, the non-zero offset situation
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has not been handled well, so it is disabled here now. */
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if (!loongarch_explicit_relocs_p (SYMBOL_PCREL64))
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return false;
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/* fall through */
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case SYMBOL_PCREL:
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/* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
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return sext_hwi (INTVAL (offset), 32) == INTVAL (offset);
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@ -2739,9 +2744,15 @@ static GTY (()) rtx loongarch_tls_symbol;
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/* Load an entry for a TLS access. */
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static rtx
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loongarch_load_tls (rtx dest, rtx sym)
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loongarch_load_tls (rtx dest, rtx sym, enum loongarch_symbol_type type)
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{
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return gen_load_tls (Pmode, dest, sym);
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/* TLS LE gets a 32 or 64 bit offset here, so one register can do it. */
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if (type == SYMBOL_TLS_LE)
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return gen_load_tls (Pmode, dest, sym);
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return loongarch_symbol_extreme_p (type)
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? gen_movdi_symbolic_off64 (dest, sym, gen_reg_rtx (DImode))
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: gen_load_tls (Pmode, dest, sym);
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}
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/* Return an instruction sequence that calls __tls_get_addr. SYM is
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@ -2773,8 +2784,6 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
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if (TARGET_CMODEL_EXTREME)
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{
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gcc_assert (TARGET_EXPLICIT_RELOCS);
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rtx tmp1 = gen_reg_rtx (Pmode);
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emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc));
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emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc));
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@ -2785,7 +2794,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
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emit_insn (gen_tls_low (Pmode, a0, high, loc));
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}
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else
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emit_insn (loongarch_load_tls (a0, loc));
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emit_insn (loongarch_load_tls (a0, loc, type));
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if (flag_plt)
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{
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@ -2852,22 +2861,28 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
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case CMODEL_EXTREME:
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{
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gcc_assert (TARGET_EXPLICIT_RELOCS);
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if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
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{
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rtx tmp1 = gen_reg_rtx (Pmode);
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rtx high = gen_reg_rtx (Pmode);
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rtx tmp1 = gen_reg_rtx (Pmode);
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rtx high = gen_reg_rtx (Pmode);
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loongarch_emit_move (high,
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gen_rtx_HIGH (Pmode, loongarch_tls_symbol));
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loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode,
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gen_rtx_REG (Pmode, 0),
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loongarch_tls_symbol));
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emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
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emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
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loongarch_emit_move (dest,
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gen_rtx_MEM (Pmode,
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gen_rtx_PLUS (Pmode,
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high, tmp1)));
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loongarch_emit_move (high,
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gen_rtx_HIGH (Pmode,
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loongarch_tls_symbol));
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loongarch_emit_move (tmp1,
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gen_rtx_LO_SUM (Pmode,
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gen_rtx_REG (Pmode, 0),
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loongarch_tls_symbol));
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emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
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emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
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loongarch_emit_move (dest,
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gen_rtx_MEM (Pmode,
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gen_rtx_PLUS (Pmode,
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high, tmp1)));
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}
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else
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emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol,
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gen_reg_rtx (DImode)));
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}
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break;
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@ -2932,8 +2947,6 @@ loongarch_legitimize_tls_address (rtx loc)
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if (TARGET_CMODEL_EXTREME)
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{
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gcc_assert (TARGET_EXPLICIT_RELOCS);
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rtx tmp3 = gen_reg_rtx (Pmode);
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emit_insn (gen_tls_low (Pmode, tmp3,
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gen_rtx_REG (Pmode, 0), tmp2));
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@ -2948,7 +2961,7 @@ loongarch_legitimize_tls_address (rtx loc)
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emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
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}
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else
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emit_insn (loongarch_load_tls (tmp1, tmp2));
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emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE));
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emit_insn (gen_add3_insn (dest, tmp1, tp));
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}
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break;
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@ -3005,14 +3018,12 @@ loongarch_legitimize_tls_address (rtx loc)
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if (TARGET_CMODEL_EXTREME)
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{
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gcc_assert (TARGET_EXPLICIT_RELOCS);
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emit_insn (gen_lui_h_lo20 (tmp1, tmp1, tmp2));
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emit_insn (gen_lui_h_hi12 (tmp1, tmp1, tmp2));
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}
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}
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else
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emit_insn (loongarch_load_tls (tmp1, tmp2));
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emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_LE));
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emit_insn (gen_add3_insn (dest, tmp1, tp));
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}
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break;
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@ -3085,7 +3096,7 @@ loongarch_force_address (rtx x, machine_mode mode)
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return x;
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}
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static bool
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bool
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loongarch_symbol_extreme_p (enum loongarch_symbol_type type)
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{
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switch (type)
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@ -3406,6 +3417,21 @@ loongarch_legitimize_move (machine_mode mode, rtx dest, rtx src)
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return true;
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}
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/* Obtain the address of the symbol through the macro instruction
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of two registers. */
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enum loongarch_symbol_type symbol_type;
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if (TARGET_64BIT && register_operand (dest, mode)
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&& loongarch_symbolic_constant_p (src, &symbol_type)
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&& loongarch_symbol_extreme_p (symbol_type))
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{
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gcc_assert (can_create_pseudo_p ());
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rtx tmp_reg = gen_reg_rtx (DImode);
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emit_insn (gen_movdi_symbolic_off64 (dest, src, tmp_reg));
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set_unique_reg_note (get_last_insn (), REG_UNUSED, tmp_reg);
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set_unique_reg_note (get_last_insn (), REG_EQUAL, src);
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return true;
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}
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return false;
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}
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@ -7462,12 +7488,22 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
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allowed, otherwise load the address into a register first. */
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if (use_sibcall_p)
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{
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insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
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if (TARGET_CMODEL_EXTREME)
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{
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emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
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insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
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}
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else
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insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
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SIBLING_CALL_P (insn) = 1;
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}
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else
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{
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loongarch_emit_move (temp1, fnaddr);
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if (TARGET_CMODEL_EXTREME)
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emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
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else
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loongarch_emit_move (temp1, fnaddr);
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emit_jump_insn (gen_indirect_jump (temp1));
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}
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@ -7572,10 +7608,6 @@ loongarch_option_override_internal (struct gcc_options *opts,
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switch (la_target.cmodel)
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{
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case CMODEL_EXTREME:
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if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
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error ("code model %qs is not compatible with %s",
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"extreme", "-mexplicit-relocs=none");
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if (opts->x_flag_plt)
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{
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if (global_options_set.x_flag_plt)
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@ -7993,14 +8025,6 @@ loongarch_handle_model_attribute (tree *node, tree name, tree arg, int,
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*no_add_attrs = true;
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return NULL_TREE;
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}
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if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
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{
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error_at (DECL_SOURCE_LOCATION (decl),
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"%qE attribute is not compatible with %s", name,
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"-mexplicit-relocs=none");
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*no_add_attrs = true;
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return NULL_TREE;
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}
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arg = TREE_VALUE (arg);
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if (TREE_CODE (arg) != STRING_CST)
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@ -82,6 +82,8 @@
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UNSPEC_SIBCALL_VALUE_MULTIPLE_INTERNAL_1
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UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1
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UNSPEC_LOAD_SYMBOL_OFFSET64
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])
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(define_c_enum "unspecv" [
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@ -2182,6 +2184,46 @@
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[(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore")
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(set_attr "mode" "DI")])
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;; Use two registers to get the global symbol address from the got table.
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;; la.global rd, rt, sym
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(define_insn_and_split "movdi_symbolic_off64"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(match_operand:DI 1 "symbolic_off64_or_reg_operand" "Yd,r"))
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(unspec:DI [(const_int 0)]
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UNSPEC_LOAD_SYMBOL_OFFSET64)
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(clobber (match_operand:DI 2 "register_operand" "=&r,r"))]
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"TARGET_64BIT && TARGET_CMODEL_EXTREME"
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{
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if (which_alternative == 1)
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return "#";
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enum loongarch_symbol_type symbol_type;
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gcc_assert (loongarch_symbolic_constant_p (operands[1], &symbol_type));
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switch (symbol_type)
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{
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case SYMBOL_PCREL64:
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return "la.local\t%0,%2,%1";
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case SYMBOL_GOT_DISP:
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return "la.global\t%0,%2,%1";
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case SYMBOL_TLS_IE:
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return "la.tls.ie\t%0,%2,%1";
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case SYMBOL_TLSGD:
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return "la.tls.gd\t%0,%2,%1";
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case SYMBOL_TLSLDM:
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return "la.tls.ld\t%0,%2,%1";
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default:
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gcc_unreachable ();
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}
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}
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"&& REG_P (operands[1]) && find_reg_note (insn, REG_UNUSED, operands[2]) != 0"
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[(set (match_dup 0) (match_dup 1))]
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""
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[(set_attr "mode" "DI")
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(set_attr "insn_count" "5")])
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;; 32-bit Integer moves
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(define_expand "movsi"
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@ -2724,7 +2766,11 @@
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}
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}
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[(set_attr "mode" "<MODE>")
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(set_attr "insn_count" "2")])
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(set (attr "insn_count")
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(if_then_else
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(match_test "TARGET_CMODEL_EXTREME")
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(const_int 4)
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(const_int 2)))])
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;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the
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;; value in the low word.
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@ -576,6 +576,18 @@
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|| symbolic_pcrel_offset_operand (op, Pmode));
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})
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(define_predicate "symbolic_off64_operand"
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(match_code "const,symbol_ref,label_ref")
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{
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enum loongarch_symbol_type type;
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return loongarch_symbolic_constant_p (op, &type)
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&& loongarch_symbol_extreme_p (type);
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})
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(define_predicate "symbolic_off64_or_reg_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "symbolic_off64_operand")))
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(define_predicate "equality_operator"
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(match_code "eq,ne"))
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8
gcc/testsuite/gcc.target/loongarch/attr-model-5.c
Normal file
8
gcc/testsuite/gcc.target/loongarch/attr-model-5.c
Normal file
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@ -0,0 +1,8 @@
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/* { dg-do compile } */
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/* { dg-options "-mexplicit-relocs=none -mcmodel=extreme -O2 -fno-pic" } */
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/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,x" } } */
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/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,y" } } */
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/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,counter" } } */
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#define ATTR_MODEL_TEST
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#include "attr-model-test.c"
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7
gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c
Normal file
7
gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c
Normal file
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@ -0,0 +1,7 @@
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/* { dg-do compile } */
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/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=none -mcmodel=extreme" } */
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/* { dg-final { scan-assembler "test:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,g" } } */
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/* { dg-final { scan-assembler "test1:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,f" } } */
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/* { dg-final { scan-assembler "test2:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,l" } } */
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#include "func-call-extreme-1.c"
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7
gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c
Normal file
7
gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c
Normal file
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@ -0,0 +1,7 @@
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/* { dg-do compile } */
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/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=none -mcmodel=extreme" } */
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/* { dg-final { scan-assembler "test:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,g" } } */
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/* { dg-final { scan-assembler "test1:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,f" } } */
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/* { dg-final { scan-assembler "test2:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,l" } } */
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#include "func-call-extreme-1.c"
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35
gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c
Normal file
35
gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c
Normal file
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@ -0,0 +1,35 @@
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/* { dg-do compile } */
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/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=none" } */
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/* { dg-final { scan-assembler "test_le:.*la.tls.le\t\\\$r\[0-9\]+,\\\.L" { target tls_native } } } */
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/* { dg-final { scan-assembler "test_ie:.*la.tls.ie\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L" { target tls_native } } } */
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/* { dg-final { scan-assembler "test_ld:.*la.tls.ld\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,__tls_get_addr" { target tls_native } } } */
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/* { dg-final { scan-assembler "test_le:.*la.tls.gd\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,__tls_get_addr" { target tls_native } } } */
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||||
|
||||
__thread int c __attribute__ ((tls_model ("local-exec")));
|
||||
__thread int d __attribute__ ((tls_model ("initial-exec")));
|
||||
__thread int e __attribute__ ((tls_model ("local-dynamic")));
|
||||
__thread int f __attribute__ ((tls_model ("global-dynamic")));
|
||||
|
||||
int
|
||||
test_le (void)
|
||||
{
|
||||
return c;
|
||||
}
|
||||
|
||||
int
|
||||
test_ie (void)
|
||||
{
|
||||
return d;
|
||||
}
|
||||
|
||||
int
|
||||
test_ld (void)
|
||||
{
|
||||
return e;
|
||||
}
|
||||
|
||||
int
|
||||
test_gd (void)
|
||||
{
|
||||
return f;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue