Refined 256/512-bit vpacksswb/vpackssdw patterns.
The packing in vpacksswb/vpackssdw is not a simple concat, it's an interweave from src1 and src2 for every 128 bit(or 64-bit for the ss_truncate result). .i.e. dst[192-255] = ss_truncate (src2[128-255]) dst[128-191] = ss_truncate (src1[128-255]) dst[64-127] = ss_truncate (src2[0-127]) dst[0-63] = ss_truncate (src1[0-127] The patch refined those patterns with an extra vec_select for the interweave. gcc/ChangeLog: PR target/110235 * config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>): Substitute with .. (sse2_packsswb<mask_name>): .. this, .. (avx2_packsswb<mask_name>): .. this and .. (avx512bw_packsswb<mask_name>): .. this. (<sse2_avx2>_packssdw<mask_name>): Substitute with .. (sse2_packssdw<mask_name>): .. this, .. (avx2_packssdw<mask_name>): .. this and .. (avx512bw_packssdw<mask_name>): .. this. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bw-vpackssdw-3.c: New test. * gcc.target/i386/avx512bw-vpacksswb-3.c: New test.
This commit is contained in:
liuhongt
parent
58e61a3ab1
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3 changed files with 252 additions and 18 deletions
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@ -17762,14 +17762,14 @@
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DONE;
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})
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(define_insn "<sse2_avx2>_packsswb<mask_name>"
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[(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>")
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(vec_concat:VI1_AVX512
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(ss_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>"))
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(ss_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))]
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"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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(define_insn "sse2_packsswb<mask_name>"
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[(set (match_operand:V16QI 0 "register_operand" "=x,Yw")
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(vec_concat:V16QI
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(ss_truncate:V8QI
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(match_operand:V8HI 1 "register_operand" "0,Yw"))
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(ss_truncate:V8QI
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(match_operand:V8HI 2 "vector_operand" "xBm,Ywm"))))]
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"TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
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"@
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packsswb\t{%2, %0|%0, %2}
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vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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@ -17777,16 +17777,93 @@
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(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1,*")
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(set_attr "prefix" "orig,<mask_prefix>")
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(set_attr "mode" "<sseinsnmode>")])
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(set_attr "mode" "TI")])
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(define_insn "<sse2_avx2>_packssdw<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,<v_Yw>")
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(vec_concat:VI2_AVX2
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(ss_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>"))
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(ss_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))]
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"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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(define_insn "avx2_packsswb<mask_name>"
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[(set (match_operand:V32QI 0 "register_operand" "=Yw")
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(vec_select:V32QI
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(vec_concat:V32QI
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(ss_truncate:V16QI
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(match_operand:V16HI 1 "register_operand" "Yw"))
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(ss_truncate:V16QI
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(match_operand:V16HI 2 "vector_operand" "Ywm")))
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)
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(const_int 16) (const_int 17)
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(const_int 18) (const_int 19)
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(const_int 20) (const_int 21)
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(const_int 22) (const_int 23)
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(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)
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(const_int 24) (const_int 25)
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(const_int 26) (const_int 27)
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(const_int 28) (const_int 29)
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(const_int 30) (const_int 31)])))]
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"TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
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"vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix" "<mask_prefix>")
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(set_attr "mode" "OI")])
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(define_insn "avx512bw_packsswb<mask_name>"
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[(set (match_operand:V64QI 0 "register_operand" "=v")
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(vec_select:V64QI
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(vec_concat:V64QI
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(ss_truncate:V32QI
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(match_operand:V32HI 1 "register_operand" "v"))
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(ss_truncate:V32QI
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(match_operand:V32HI 2 "vector_operand" "vm")))
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)
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(const_int 32) (const_int 33)
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(const_int 34) (const_int 35)
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(const_int 36) (const_int 37)
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(const_int 38) (const_int 39)
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(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)
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(const_int 40) (const_int 41)
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(const_int 42) (const_int 43)
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(const_int 44) (const_int 45)
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(const_int 46) (const_int 47)
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(const_int 16) (const_int 17)
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(const_int 18) (const_int 19)
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(const_int 20) (const_int 21)
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(const_int 22) (const_int 23)
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(const_int 48) (const_int 49)
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(const_int 50) (const_int 51)
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(const_int 52) (const_int 53)
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(const_int 54) (const_int 55)
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(const_int 24) (const_int 25)
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(const_int 26) (const_int 27)
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(const_int 28) (const_int 29)
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(const_int 30) (const_int 31)
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(const_int 56) (const_int 57)
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(const_int 58) (const_int 59)
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(const_int 60) (const_int 61)
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(const_int 62) (const_int 63)])))]
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"TARGET_AVX512BW"
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"vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix" "<mask_prefix>")
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(set_attr "mode" "XI")])
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(define_insn "sse2_packssdw<mask_name>"
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[(set (match_operand:V8HI 0 "register_operand" "=x,Yw")
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(vec_concat:V8HI
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(ss_truncate:V4HI
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(match_operand:V4SI 1 "register_operand" "0,Yw"))
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(ss_truncate:V4HI
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(match_operand:V4SI 2 "vector_operand" "xBm,Ywm"))))]
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"TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
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"@
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packssdw\t{%2, %0|%0, %2}
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vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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@ -17794,7 +17871,59 @@
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(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1,*")
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(set_attr "prefix" "orig,<mask_prefix>")
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(set_attr "mode" "<sseinsnmode>")])
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(set_attr "mode" "TI")])
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(define_insn "avx2_packssdw<mask_name>"
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[(set (match_operand:V16HI 0 "register_operand" "=Yw")
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(vec_select:V16HI
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(vec_concat:V16HI
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(ss_truncate:V8HI
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(match_operand:V8SI 1 "register_operand" "Yw"))
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(ss_truncate:V8HI
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(match_operand:V8SI 2 "vector_operand" "Ywm")))
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)])))]
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"TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
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"vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix" "<mask_prefix>")
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(set_attr "mode" "OI")])
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(define_insn "avx512bw_packssdw<mask_name>"
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[(set (match_operand:V32HI 0 "register_operand" "=v")
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(vec_select:V32HI
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(vec_concat:V32HI
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(ss_truncate:V16HI
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(match_operand:V16SI 1 "register_operand" "v"))
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(ss_truncate:V16HI
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(match_operand:V16SI 2 "vector_operand" "vm")))
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 16) (const_int 17)
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(const_int 18) (const_int 19)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)
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(const_int 20) (const_int 21)
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(const_int 22) (const_int 23)
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(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 24) (const_int 25)
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(const_int 26) (const_int 27)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)
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(const_int 28) (const_int 29)
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(const_int 30) (const_int 31)])))]
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"TARGET_AVX512BW"
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"vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix" "<mask_prefix>")
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(set_attr "mode" "XI")])
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;; This instruction does unsigned saturation of signed source
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;; and is different from generic us_truncate RTX.
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55
gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c
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55
gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c
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@ -0,0 +1,55 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -mavx512bw" } */
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/* { dg-require-effective-target avx512bw } */
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#define AVX512BW
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#include "avx512f-helper.h"
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#define DST_SIZE (AVX512F_LEN / 16)
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#define SRC_SIZE (AVX512F_LEN / 32)
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#include "limits.h"
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#include "avx512f-mask-type.h"
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static short
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int_to_short (int iVal)
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{
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short sVal;
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if (iVal < -32768)
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sVal = -32768;
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else if (iVal > 32767)
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sVal = 32767;
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else
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sVal = iVal;
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return sVal;
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}
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void
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TEST (void)
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{
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union512i_d s1, s2;
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union512i_w res1;
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short dst_ref[32];
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int i;
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s1.x = _mm512_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -65000);
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s2.x = _mm512_set_epi32 (80, 40, 31, 21, 10, 99, 74, -65000, 2, 3, 4, 5, 65010, 21, 31, 91);
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res1.x = _mm512_packs_epi32 (s1.x, s2.x);
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for (int i = 0; i != 4; i++)
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{
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dst_ref[i] = int_to_short (s1.a[i]);
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dst_ref[i + 4] = int_to_short (s2.a[i]);
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dst_ref[i + 8] = int_to_short (s1.a[i + 4]);
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dst_ref[i + 12] = int_to_short (s2.a[i + 4]);
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dst_ref[i + 16] = int_to_short (s1.a[i + 8]);
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dst_ref[i + 20] = int_to_short (s2.a[i + 8]);
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dst_ref[i + 24] = int_to_short (s1.a[i + 12]);
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dst_ref[i + 28] = int_to_short (s2.a[i + 12]);
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}
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if (check_union512i_w (res1, dst_ref))
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abort ();
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}
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50
gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c
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50
gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c
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@ -0,0 +1,50 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -mavx512bw" } */
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/* { dg-require-effective-target avx512bw } */
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#define AVX512BW
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#include "avx512f-helper.h"
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static char
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short_to_byte (short iVal)
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{
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short sVal;
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if (iVal < -128)
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sVal = -128;
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else if (iVal > 127)
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sVal = 127;
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else
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sVal = iVal;
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return sVal;
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}
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void
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TEST (void)
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{
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union512i_w s1, s2;
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union512i_b res1;
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char dst_ref[64];
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int i;
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s1.x = _mm512_set_epi16 (1, 2, 3, 4, 650, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -650,
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128, 230, -112, -128, -3, -4, -7, 9, 10, 11, 12, 13, -223, 10, 8, 11);
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s2.x = _mm512_set_epi16 (80, 40, 31, 21, 10, 99, 74, -650, 2, 3, 4, 5, 650, 21, 31, 91,
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280, -140, 310, 20, 9, 98, 73, -651, 3, 4, 5, 6, 651, 22, 32, 92);
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res1.x = _mm512_packs_epi16 (s1.x, s2.x);
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for (int i = 0; i != 8; i++)
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{
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dst_ref[i] = short_to_byte (s1.a[i]);
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dst_ref[i + 8] = short_to_byte (s2.a[i]);
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dst_ref[i + 16] = short_to_byte (s1.a[i + 8]);
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dst_ref[i + 24] = short_to_byte (s2.a[i + 8]);
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dst_ref[i + 32] = short_to_byte (s1.a[i + 16]);
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dst_ref[i + 40] = short_to_byte (s2.a[i + 16]);
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dst_ref[i + 48] = short_to_byte (s1.a[i + 24]);
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dst_ref[i + 56] = short_to_byte (s2.a[i + 24]);
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}
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if (check_union512i_b (res1, dst_ref))
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abort ();
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}
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