diff --git a/gcc/dse.c b/gcc/dse.c
index d65266b5476..651e6e7e71e 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1757,8 +1757,7 @@ find_shift_sequence (poly_int64 access_size,
      the machine.  */
 
   opt_scalar_int_mode new_mode_iter;
-  FOR_EACH_MODE_FROM (new_mode_iter,
-		      smallest_int_mode_for_size (GET_MODE_BITSIZE (read_mode)))
+  FOR_EACH_MODE_IN_CLASS (new_mode_iter, MODE_INT)
     {
       rtx target, new_reg, new_lhs;
       rtx_insn *shift_seq, *insn;
@@ -1767,6 +1766,8 @@ find_shift_sequence (poly_int64 access_size,
       new_mode = new_mode_iter.require ();
       if (GET_MODE_BITSIZE (new_mode) > BITS_PER_WORD)
 	break;
+      if (maybe_lt (GET_MODE_SIZE (new_mode), GET_MODE_SIZE (read_mode)))
+	continue;
 
       /* Try a wider mode if truncating the store mode to NEW_MODE
 	 requires a real instruction.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr98037.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr98037.c
new file mode 100644
index 00000000000..b91e940b18e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr98037.c
@@ -0,0 +1,6 @@
+/* { dg-options "-msve-vector-bits=1024 -O3" } */
+
+typedef __SVInt8_t vec __attribute__((arm_sve_vector_bits(1024)));
+struct pair { vec v[2]; };
+void use (struct pair *);
+vec f (struct pair p) { vec v = p.v[1]; use (&p); return v; }