LoongArch: Don't split the instructions containing relocs for extreme code model.
The ABI mandates the pcalau12i/addi.d/lu32i.d/lu52i.d instructions for
addressing a symbol to be adjacent. So model them as "one large
instruction", i.e. define_insn, with two output registers. The real
address is the sum of these two registers.
The advantage of this approach is the RTL passes can still use ldx/stx
instructions to skip an addi.d instruction.
gcc/ChangeLog:
* config/loongarch/loongarch.md (unspec): Add
UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
(la_pcrel64_two_parts): New define_insn.
* config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
typo in the comment.
(loongarch_call_tls_get_addr): If -mcmodel=extreme
-mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
note to allow CSE addressing __tls_get_addr.
(loongarch_legitimize_tls_address): If -mcmodel=extreme
-mexplicit-relocs={always,auto}, address TLS IE symbols with
la_pcrel64_two_parts.
(loongarch_split_symbol): If -mcmodel=extreme
-mexplicit-relocs={always,auto}, address symbols with
la_pcrel64_two_parts.
(loongarch_output_mi_thunk): Clean up unreachable code. If
-mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
thunks with la_pcrel64_two_parts.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/func-call-extreme-1.c (dg-options):
Use -O2 instead of -O0 to ensure the pcalau12i/addi/lu32i/lu52i
instruction sequences are not reordered by the compiler.
(NOIPA): Disallow interprocedural optimizations.
* gcc.target/loongarch/func-call-extreme-2.c: Remove the content
duplicated from func-call-extreme-1.c, include it instead.
(dg-options): Likewise.
* gcc.target/loongarch/func-call-extreme-3.c (dg-options):
Likewise.
* gcc.target/loongarch/func-call-extreme-4.c (dg-options):
Likewise.
* gcc.target/loongarch/cmodel-extreme-1.c: New test.
* gcc.target/loongarch/cmodel-extreme-2.c: New test.
* g++.target/loongarch/cmodel-extreme-mi-thunk-1.C: New test.
* g++.target/loongarch/cmodel-extreme-mi-thunk-2.C: New test.
* g++.target/loongarch/cmodel-extreme-mi-thunk-3.C: New test.
This commit is contained in:
Xi Ruoyao
Lulu Cheng
parent
3932899a83
commit
f72586e5b9
11 changed files with 154 additions and 92 deletions
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@ -2737,7 +2737,7 @@ loongarch_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
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return plus_constant (Pmode, reg, offset);
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}
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/* The __tls_get_attr symbol. */
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/* The __tls_get_addr symbol. */
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static GTY (()) rtx loongarch_tls_symbol;
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/* Load an entry for a TLS access. */
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@ -2777,20 +2777,22 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
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if (loongarch_explicit_relocs_p (type))
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{
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/* Split tls symbol to high and low. */
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rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
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high = loongarch_force_temporary (tmp, high);
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if (TARGET_CMODEL_EXTREME)
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{
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rtx tmp1 = gen_reg_rtx (Pmode);
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emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc));
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emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc));
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emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loc));
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emit_move_insn (a0, gen_rtx_PLUS (Pmode, high, tmp1));
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rtx part1 = gen_reg_rtx (Pmode);
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rtx part2 = gen_reg_rtx (Pmode);
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emit_insn (gen_la_pcrel64_two_parts (part1, part2, loc));
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emit_move_insn (a0, gen_rtx_PLUS (Pmode, part1, part2));
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}
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else
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emit_insn (gen_tls_low (Pmode, a0, high, loc));
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{
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/* Split tls symbol to high and low. */
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rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
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high = loongarch_force_temporary (tmp, high);
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emit_insn (gen_tls_low (Pmode, a0, high, loc));
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}
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}
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else
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emit_insn (loongarch_load_tls (a0, loc, type));
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@ -2872,22 +2874,28 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
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{
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if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
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{
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rtx tmp1 = gen_reg_rtx (Pmode);
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rtx high = gen_reg_rtx (Pmode);
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gcc_assert (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE);
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loongarch_emit_move (high,
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gen_rtx_HIGH (Pmode,
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loongarch_tls_symbol));
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loongarch_emit_move (tmp1,
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gen_rtx_LO_SUM (Pmode,
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gen_rtx_REG (Pmode, 0),
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rtx part1 = gen_reg_rtx (Pmode);
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rtx part2 = gen_reg_rtx (Pmode);
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emit_insn (gen_la_pcrel64_two_parts (part1, part2,
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loongarch_tls_symbol));
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emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
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emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
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loongarch_emit_move (dest,
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gen_rtx_MEM (Pmode,
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gen_rtx_PLUS (Pmode,
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high, tmp1)));
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loongarch_emit_move (
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dest,
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gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode,
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part1,
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part2)));
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/* Put an REG_EQUAL note here to allow CSE (storing
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part1 + part2, i.e. the address of tls_get_addr into
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a saved register and use it for multiple TLS
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accesses). */
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rtx sum = gen_rtx_UNSPEC (
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Pmode, gen_rtvec (1, loongarch_tls_symbol),
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UNSPEC_ADDRESS_FIRST
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+ loongarch_classify_symbol (loongarch_tls_symbol));
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set_unique_reg_note (get_last_insn (), REG_EQUAL, sum);
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}
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else
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emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol,
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@ -2950,24 +2958,30 @@ loongarch_legitimize_tls_address (rtx loc)
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dest = gen_reg_rtx (Pmode);
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if (loongarch_explicit_relocs_p (SYMBOL_TLS_IE))
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{
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tmp3 = gen_reg_rtx (Pmode);
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rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
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high = loongarch_force_temporary (tmp3, high);
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if (TARGET_CMODEL_EXTREME)
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{
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rtx tmp3 = gen_reg_rtx (Pmode);
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emit_insn (gen_tls_low (Pmode, tmp3,
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gen_rtx_REG (Pmode, 0), tmp2));
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emit_insn (gen_lui_h_lo20 (tmp3, tmp3, tmp2));
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emit_insn (gen_lui_h_hi12 (tmp3, tmp3, tmp2));
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gcc_assert (la_opt_explicit_relocs
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!= EXPLICIT_RELOCS_NONE);
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rtx part1 = gen_reg_rtx (Pmode);
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rtx part2 = gen_reg_rtx (Pmode);
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emit_insn (gen_la_pcrel64_two_parts (part1, part2,
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tmp2));
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emit_move_insn (tmp1,
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gen_rtx_MEM (Pmode,
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gen_rtx_PLUS (Pmode,
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high, tmp3)));
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part1,
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part2)));
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}
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else
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emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
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{
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tmp3 = gen_reg_rtx (Pmode);
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rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
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high = loongarch_force_temporary (tmp3, high);
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emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
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}
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}
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else
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emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE));
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@ -3146,24 +3160,23 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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|| !loongarch_split_symbol_type (symbol_type))
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return false;
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rtx high, temp1 = NULL;
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rtx high;
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if (temp == NULL)
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temp = gen_reg_rtx (Pmode);
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/* Get the 12-31 bits of the address. */
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high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
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high = loongarch_force_temporary (temp, high);
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if (loongarch_symbol_extreme_p (symbol_type) && can_create_pseudo_p ())
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{
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gcc_assert (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE);
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temp1 = gen_reg_rtx (Pmode);
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emit_move_insn (temp1, gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 0),
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addr));
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emit_insn (gen_lui_h_lo20 (temp1, temp1, addr));
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emit_insn (gen_lui_h_hi12 (temp1, temp1, addr));
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high = gen_reg_rtx (Pmode);
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emit_insn (gen_la_pcrel64_two_parts (high, temp, addr));
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}
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else
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{
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/* Get the 12-31 bits of the address. */
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high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
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high = loongarch_force_temporary (temp, high);
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}
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if (low_out)
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@ -3172,7 +3185,7 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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case SYMBOL_PCREL64:
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if (can_create_pseudo_p ())
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{
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*low_out = gen_rtx_PLUS (Pmode, high, temp1);
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*low_out = gen_rtx_PLUS (Pmode, high, temp);
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break;
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}
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/* fall through */
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@ -3184,7 +3197,8 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
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/* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
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{
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if (TARGET_CMODEL_EXTREME && can_create_pseudo_p ())
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*low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high, temp1));
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*low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high,
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temp));
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else
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{
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rtx low = gen_rtx_LO_SUM (Pmode, high, addr);
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@ -7497,21 +7511,24 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
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allowed, otherwise load the address into a register first. */
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if (use_sibcall_p)
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{
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if (TARGET_CMODEL_EXTREME)
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{
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emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
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insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
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}
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else
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insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
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/* If TARGET_CMODEL_EXTREME, we cannot do a direct jump at all
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and const_call_insn_operand should have returned false. */
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gcc_assert (!TARGET_CMODEL_EXTREME);
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insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
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SIBLING_CALL_P (insn) = 1;
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}
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else
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{
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if (TARGET_CMODEL_EXTREME)
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if (!TARGET_CMODEL_EXTREME)
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loongarch_emit_move (temp1, fnaddr);
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else if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
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emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
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else
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loongarch_emit_move (temp1, fnaddr);
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{
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emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
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emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
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}
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emit_jump_insn (gen_indirect_jump (temp1));
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}
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@ -84,6 +84,8 @@
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UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1
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UNSPEC_LOAD_SYMBOL_OFFSET64
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UNSPEC_LA_PCREL_64_PART1
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UNSPEC_LA_PCREL_64_PART2
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])
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(define_c_enum "unspecv" [
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@ -2224,6 +2226,24 @@
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[(set_attr "mode" "DI")
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(set_attr "insn_count" "5")])
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;; The 64-bit PC-relative part of address loading.
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;; Note that the psABI does not allow splitting it.
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(define_insn "la_pcrel64_two_parts"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_operand:DI 2 "") (pc)] UNSPEC_LA_PCREL_64_PART1))
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(set (match_operand:DI 1 "register_operand" "=r")
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(unspec:DI [(match_dup 2) (pc)] UNSPEC_LA_PCREL_64_PART2))]
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"TARGET_ABI_LP64 && la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE"
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{
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return "pcalau12i\t%0,%r2\n\t"
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"addi.d\t%1,$r0,%L2\n\t"
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"lu32i.d\t%1,%R2\n\t"
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"lu52i.d\t%1,%1,%H2";
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}
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[(set_attr "move_type" "move")
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(set_attr "mode" "DI")
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(set_attr "length" "16")])
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;; 32-bit Integer moves
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(define_expand "movsi"
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@ -0,0 +1,11 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -mdirect-extern-access" } */
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struct A {
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virtual ~A();
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};
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struct B : virtual A {};
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void var() { B(); }
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/* { dg-final { scan-assembler "pcalau12i\t\[^\n\]*%pc_hi20\\(\\.LTHUNK0\\)\n\taddi\\.d\t\[^\n\]*%pc_lo12\\(\\\.LTHUNK0\\)\n\tlu32i\\.d\t\[^\n\]*%pc64_lo20\\(\\.LTHUNK0\\)\n\tlu52i\\.d\t\[^\n\]*%pc64_hi12\\(\\.LTHUNK0\\)" } } */
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@ -0,0 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -mdirect-extern-access" } */
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#include "cmodel-extreme-mi-thunk-1.C"
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/* { dg-final { scan-assembler "pcalau12i\t\[^\n\]*%pc_hi20\\(\\.LTHUNK0\\)\n\taddi\\.d\t\[^\n\]*%pc_lo12\\(\\\.LTHUNK0\\)\n\tlu32i\\.d\t\[^\n\]*%pc64_lo20\\(\\.LTHUNK0\\)\n\tlu52i\\.d\t\[^\n\]*%pc64_hi12\\(\\.LTHUNK0\\)" } } */
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@ -0,0 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=none -mdirect-extern-access" } */
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#include "cmodel-extreme-mi-thunk-1.C"
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/* { dg-final { scan-assembler "la.local\t\[^\n\]*\\.LTHUNK0" } } */
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18
gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
Normal file
18
gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
Normal file
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@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -fdump-rtl-final" } */
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int a;
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extern int b;
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__thread int c __attribute__ ((tls_model ("local-exec")));
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__thread int d __attribute__ ((tls_model ("initial-exec")));
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__thread int e __attribute__ ((tls_model ("local-dynamic")));
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__thread int f __attribute__ ((tls_model ("global-dynamic")));
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void
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test (void)
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{
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a = b + c + d + e + f;
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}
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/* a, b, d, e, f, and __tls_get_addr. */
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/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */
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7
gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c
Normal file
7
gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c
Normal file
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@ -0,0 +1,7 @@
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/* { dg-do compile } */
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/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -fdump-rtl-final" } */
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#include "cmodel-extreme-1.c"
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/* a, b, d, e, f, and __tls_get_addr. */
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/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */
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@ -1,31 +1,33 @@
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/* { dg-do compile } */
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/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
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/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
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/* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
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/* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
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/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
|
||||
|
||||
#define NOIPA __attribute__ ((noipa))
|
||||
|
||||
extern void g (void);
|
||||
void
|
||||
NOIPA void
|
||||
f (void)
|
||||
{}
|
||||
|
||||
static void
|
||||
NOIPA static void
|
||||
l (void)
|
||||
{}
|
||||
|
||||
void
|
||||
NOIPA void
|
||||
test (void)
|
||||
{
|
||||
g ();
|
||||
}
|
||||
|
||||
void
|
||||
NOIPA void
|
||||
test1 (void)
|
||||
{
|
||||
f ();
|
||||
}
|
||||
|
||||
void
|
||||
NOIPA void
|
||||
test2 (void)
|
||||
{
|
||||
l ();
|
||||
|
|
|
|||
|
|
@ -1,32 +1,7 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
|
||||
/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
|
||||
/* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
|
||||
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
|
||||
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
|
||||
|
||||
extern void g (void);
|
||||
void
|
||||
f (void)
|
||||
{}
|
||||
|
||||
static void
|
||||
l (void)
|
||||
{}
|
||||
|
||||
void
|
||||
test (void)
|
||||
{
|
||||
g ();
|
||||
}
|
||||
|
||||
void
|
||||
test1 (void)
|
||||
{
|
||||
f ();
|
||||
}
|
||||
|
||||
void
|
||||
test2 (void)
|
||||
{
|
||||
l ();
|
||||
}
|
||||
#include "func-call-extreme-1.c"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
|
||||
/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
|
||||
/* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
|
||||
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
|
||||
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
|
||||
/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
|
||||
/* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
|
||||
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
|
||||
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue