RISC-V: Fix incorrect index(offset) of gather/scatter
I suddenly discovered I made a mistake that was lucky un-exposed. https://godbolt.org/z/c3jzrh7or GCC is using 32 bit index offset: vsll.vi v1,v1,2 vsetvli zero,a5,e32,m1,ta,ma vluxei32.v v1,(a1),v1 This is wrong since v1 may overflow 32bit after vsll.vi. After this patch: vsext.vf2 v8,v4 vsll.vi v8,v8,2 vluxei64.v v8,(a1),v8 Same as Clang. Regression passed. Ok for trunk ? gcc/ChangeLog: * config/riscv/autovec.md: Fix index bug. * config/riscv/riscv-protos.h (gather_scatter_valid_offset_mode_p): New function. * config/riscv/riscv-v.cc (expand_gather_scatter): Fix index bug. (gather_scatter_valid_offset_mode_p): New function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/offset_extend-1.c: New test.
This commit is contained in:
Juzhe-Zhong
Pan Li
parent
d1e5566685
commit
f6c5e247b2
4 changed files with 39 additions and 17 deletions
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@ -59,7 +59,7 @@
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(match_operand:<RATIO64:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO64:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -74,7 +74,7 @@
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(match_operand:<RATIO32:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO32:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -89,7 +89,7 @@
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(match_operand:<RATIO16:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO16:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -104,7 +104,7 @@
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(match_operand:<RATIO8:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO8:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -119,7 +119,7 @@
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(match_operand:<RATIO4:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO4:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -134,7 +134,7 @@
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(match_operand:<RATIO2:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO2:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -153,7 +153,7 @@
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(match_operand:<RATIO1:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO1:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, true);
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DONE;
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@ -172,7 +172,7 @@
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(match_operand:<RATIO64:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO64:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -187,7 +187,7 @@
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(match_operand:<RATIO32:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO32:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -202,7 +202,7 @@
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(match_operand:<RATIO16:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO16:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -217,7 +217,7 @@
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(match_operand:<RATIO8:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO8:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -232,7 +232,7 @@
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(match_operand:<RATIO4:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO4:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -247,7 +247,7 @@
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(match_operand:<RATIO2:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO2:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -266,7 +266,7 @@
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(match_operand:<RATIO1:VM> 5 "vector_mask_operand")
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(match_operand 6 "autovec_length_operand")
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(match_operand 7 "const_0_operand")]
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"TARGET_VECTOR"
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"TARGET_VECTOR && riscv_vector::gather_scatter_valid_offset_mode_p (<RATIO1:MODE>mode)"
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{
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riscv_vector::expand_gather_scatter (operands, false);
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DONE;
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@ -544,6 +544,7 @@ opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
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unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
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bool cmp_lmul_le_one (machine_mode);
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bool cmp_lmul_gt_one (machine_mode);
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bool gather_scatter_valid_offset_mode_p (machine_mode);
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}
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/* We classify builtin types into two classes:
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@ -3491,15 +3491,14 @@ expand_gather_scatter (rtx *ops, bool is_load)
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machine_mode vec_mode = GET_MODE (vec_reg);
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machine_mode idx_mode = GET_MODE (vec_offset);
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scalar_mode inner_vec_mode = GET_MODE_INNER (vec_mode);
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scalar_mode inner_idx_mode = GET_MODE_INNER (idx_mode);
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unsigned inner_vsize = GET_MODE_BITSIZE (inner_vec_mode);
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unsigned inner_offsize = GET_MODE_BITSIZE (inner_idx_mode);
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poly_int64 nunits = GET_MODE_NUNITS (vec_mode);
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poly_int64 value;
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bool is_vlmax = poly_int_rtx_p (len, &value) && known_eq (value, nunits);
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if (inner_offsize < inner_vsize)
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/* Extend the offset element to address width. */
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if (inner_offsize < BITS_PER_WORD)
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{
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/* 7.2. Vector Load/Store Addressing Modes.
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If the vector offset elements are narrower than XLEN, they are
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@ -3796,6 +3795,14 @@ cmp_lmul_gt_one (machine_mode mode)
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return false;
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}
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/* Return true if the gather/scatter offset mode is valid. */
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bool
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gather_scatter_valid_offset_mode_p (machine_mode mode)
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{
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machine_mode new_mode;
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return get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists (&new_mode);
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}
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/* We don't have to convert the floating point to integer when the
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mantissa is zero. Thus, ther will be a limitation for both the
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single and double precision floating point. There will be no
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@ -0,0 +1,14 @@
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/* { dg-do compile } */
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/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
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void
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f (int *restrict y, int *restrict x, int *restrict indices, int n)
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{
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for (int i = 0; i < n; ++i)
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y[i] = x[indices[i]] + 1;
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}
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/* { dg-final { scan-assembler {vluxei64\.v} } } */
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/* { dg-final { scan-assembler {vsll\.vi} } } */
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/* { dg-final { scan-assembler {vsext\.vf2} } } */
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/* { dg-final { scan-assembler-not {vluxei32\.v} } } */
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