New .md construct: define_insn_and_rewrite
Several SVE patterns need define_insn_and_splits that generate the same insn_code, but with different operands. That's probably a niche requirement, but it's cropping up often enough on the ACLE branch that I think it would be good to have a syntactic sugar for it. This patch therefore adds a new construct called define_insn_and_rewrite. It's basically a define_insn_and_split with an implicit split pattern, obtained by copying the insn pattern and replacing match_operands with match_dups and match_operators with match_op_dups. 2019-05-31 Richard Sandiford <richard.sandiford@arm.com> gcc/ * doc/md.texi: Document define_insn_and_rewrite. * rtl.def (DEFINE_INSN_AND_REWRITE): New rtx code. * gensupport.c (queue_elem): Update comment. (replace_operands_with_dups): New function. (gen_rewrite_sequence): Likewise. (process_rtx): Handle DEFINE_INSN_AND_REWRITE. * read-rtl.c (apply_subst_iterator): Likewise. (add_condition_to_rtx, named_rtx_p): Likewise. (rtx_reader::read_rtx_operand): Likewise. * config/aarch64/aarch64-sve.md (while_ult<GPI:mode><PRED_ALL:mode>_cc): Rename to... (*while_ult<GPI:mode><PRED_ALL:mode>_cc): ...this and use define_insn_and_rewrite. (*cond_<optab><mode>_any): Turn into define_insn_and_rewrites. Remove separate define_split. From-SVN: r271815
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
b1bb4869e2
commit
f4fde1b378
6 changed files with 249 additions and 62 deletions
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@ -1,3 +1,21 @@
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2019-05-31 Richard Sandiford <richard.sandiford@arm.com>
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* doc/md.texi: Document define_insn_and_rewrite.
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* rtl.def (DEFINE_INSN_AND_REWRITE): New rtx code.
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* gensupport.c (queue_elem): Update comment.
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(replace_operands_with_dups): New function.
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(gen_rewrite_sequence): Likewise.
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(process_rtx): Handle DEFINE_INSN_AND_REWRITE.
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* read-rtl.c (apply_subst_iterator): Likewise.
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(add_condition_to_rtx, named_rtx_p): Likewise.
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(rtx_reader::read_rtx_operand): Likewise.
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* config/aarch64/aarch64-sve.md
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(while_ult<GPI:mode><PRED_ALL:mode>_cc): Rename to...
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(*while_ult<GPI:mode><PRED_ALL:mode>_cc): ...this and use
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define_insn_and_rewrite.
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(*cond_<optab><mode>_any): Turn into define_insn_and_rewrites.
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Remove separate define_split.
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2019-05-31 Jan Hubicka <jh@suse.cz>
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* tree-ssa-alias.c (type_has_components_p): New function.
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@ -1345,7 +1345,7 @@
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;; WHILELO sets the flags in the same way as a PTEST with a PTRUE GP.
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;; Handle the case in which both results are useful. The GP operand
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;; to the PTEST isn't needed, so we allow it to be anything.
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(define_insn_and_split "while_ult<GPI:mode><PRED_ALL:mode>_cc"
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(define_insn_and_rewrite "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(unspec:SI [(match_operand:PRED_ALL 1)
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@ -1364,12 +1364,8 @@
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;; Force the compiler to drop the unused predicate operand, so that we
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;; don't have an unnecessary PTRUE.
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"&& !CONSTANT_P (operands[1])"
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[(const_int 0)]
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{
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emit_insn (gen_while_ult<GPI:mode><PRED_ALL:mode>_cc
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(operands[0], CONSTM1_RTX (<MODE>mode),
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operands[2], operands[3]));
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DONE;
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operands[1] = CONSTM1_RTX (<MODE>mode);
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}
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)
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@ -2003,7 +1999,7 @@
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)
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;; Synthetic predications with select unmatched.
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(define_insn "*cond_<optab><mode>_any"
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(define_insn_and_rewrite "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_I 0 "register_operand" "=&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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@ -2012,11 +2008,20 @@
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(match_operand:SVE_I 3 "register_operand" "w"))
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(match_operand:SVE_I 4 "register_operand" "w")]
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UNSPEC_SEL))]
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"TARGET_SVE"
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"TARGET_SVE
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&& !(rtx_equal_p (operands[0], operands[4])
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|| rtx_equal_p (operands[2], operands[4])
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|| rtx_equal_p (operands[3], operands[4]))"
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"#"
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"&& reload_completed"
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{
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emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[2],
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operands[4], operands[1]));
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operands[4] = operands[2] = operands[0];
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}
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)
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(define_insn "*cond_<optab><mode>_any"
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(define_insn_and_rewrite "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_SDI 0 "register_operand" "=&w")
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(unspec:SVE_SDI
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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@ -2025,33 +2030,17 @@
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(match_operand:SVE_SDI 3 "register_operand" "w"))
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(match_operand:SVE_SDI 4 "register_operand" "w")]
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UNSPEC_SEL))]
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"TARGET_SVE"
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"#"
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)
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(define_split
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand")
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(match_operator:SVE_I 5 "aarch64_sve_any_binary_operator"
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[(match_operand:SVE_I 2 "register_operand")
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(match_operand:SVE_I 3 "register_operand")])
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(match_operand:SVE_I 4 "register_operand")]
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UNSPEC_SEL))]
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"TARGET_SVE && reload_completed
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"TARGET_SVE
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&& !(rtx_equal_p (operands[0], operands[4])
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|| rtx_equal_p (operands[2], operands[4])
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|| rtx_equal_p (operands[3], operands[4]))"
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; Not matchable by any one insn or movprfx insn. We need a separate select.
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[(set (match_dup 0)
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(unspec:SVE_I [(match_dup 1) (match_dup 2) (match_dup 4)]
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UNSPEC_SEL))
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(set (match_dup 0)
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(unspec:SVE_I
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[(match_dup 1)
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(match_op_dup 5 [(match_dup 0) (match_dup 3)])
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(match_dup 0)]
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UNSPEC_SEL))]
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"#"
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"&& reload_completed"
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{
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emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[2],
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operands[4], operands[1]));
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operands[4] = operands[2] = operands[0];
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}
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)
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;; Set operand 0 to the last active element in operand 3, or to tied
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@ -2957,7 +2946,7 @@
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)
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;; Synthetic predication of floating-point operations with select unmatched.
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(define_insn_and_split "*cond_<optab><mode>_any"
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(define_insn_and_rewrite "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_F 0 "register_operand" "=&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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@ -2974,14 +2963,11 @@
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|| rtx_equal_p (operands[2], operands[4])
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|| rtx_equal_p (operands[3], operands[4]))"
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; Not matchable by any one insn or movprfx insn. We need a separate select.
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[(set (match_dup 0)
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(unspec:SVE_F [(match_dup 1) (match_dup 2) (match_dup 4)] UNSPEC_SEL))
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(set (match_dup 0)
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(unspec:SVE_F
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[(match_dup 1)
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(unspec:SVE_F [(match_dup 0) (match_dup 3)] SVE_COND_FP_BINARY)
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(match_dup 0)]
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UNSPEC_SEL))]
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{
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emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[2],
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operands[4], operands[1]));
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operands[4] = operands[2] = operands[0];
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}
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)
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;; Predicated floating-point ternary operations with select.
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@ -3044,7 +3030,7 @@
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;; Predicated floating-point ternary operations in which the value for
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;; inactive lanes is distinct from the other inputs.
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(define_insn_and_split "*cond_<optab><mode>_any"
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(define_insn_and_rewrite "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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@ -3066,16 +3052,11 @@
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"&& reload_completed
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&& !CONSTANT_P (operands[5])
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&& !rtx_equal_p (operands[0], operands[5])"
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[(set (match_dup 0)
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(unspec:SVE_F [(match_dup 1) (match_dup 4) (match_dup 5)] UNSPEC_SEL))
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(set (match_dup 0)
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(unspec:SVE_F
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[(match_dup 1)
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(unspec:SVE_F [(match_dup 2) (match_dup 3) (match_dup 0)]
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SVE_COND_FP_TERNARY)
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(match_dup 0)]
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UNSPEC_SEL))]
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""
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{
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emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[4],
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operands[5], operands[1]));
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operands[5] = operands[4] = operands[0];
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}
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[(set_attr "movprfx" "yes")]
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)
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113
gcc/doc/md.texi
113
gcc/doc/md.texi
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@ -8498,6 +8498,119 @@ functionality as two separate @code{define_insn} and @code{define_split}
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patterns. It exists for compactness, and as a maintenance tool to prevent
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having to ensure the two patterns' templates match.
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@findex define_insn_and_rewrite
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It is sometimes useful to have a @code{define_insn_and_split}
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that replaces specific operands of an instruction but leaves the
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rest of the instruction pattern unchanged. You can do this directly
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with a @code{define_insn_and_split}, but it requires a
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@var{new-insn-pattern-1} that repeats most of the original @var{insn-pattern}.
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There is also the complication that an implicit @code{parallel} in
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@var{insn-pattern} must become an explicit @code{parallel} in
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@var{new-insn-pattern-1}, which is easy to overlook.
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A simpler alternative is to use @code{define_insn_and_rewrite}, which
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is a form of @code{define_insn_and_split} that automatically generates
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@var{new-insn-pattern-1} by replacing each @code{match_operand}
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in @var{insn-pattern} with a corresponding @code{match_dup}, and each
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@code{match_operator} in the pattern with a corresponding @code{match_op_dup}.
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The arguments are otherwise identical to @code{define_insn_and_split}:
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@smallexample
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(define_insn_and_rewrite
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[@var{insn-pattern}]
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"@var{condition}"
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"@var{output-template}"
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"@var{split-condition}"
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"@var{preparation-statements}"
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[@var{insn-attributes}])
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@end smallexample
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The @code{match_dup}s and @code{match_op_dup}s in the new
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instruction pattern use any new operand values that the
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@var{preparation-statements} store in the @code{operands} array,
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as for a normal @code{define_insn_and_split}. @var{preparation-statements}
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can also emit additional instructions before the new instruction.
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They can even emit an entirely different sequence of instructions and
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use @code{DONE} to avoid emitting a new form of the original
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instruction.
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The split in a @code{define_insn_and_rewrite} is only intended
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to apply to existing instructions that match @var{insn-pattern}.
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@var{split-condition} must therefore start with @code{&&},
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so that the split condition applies on top of @var{condition}.
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Here is an example from the AArch64 SVE port, in which operand 1 is
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known to be equivalent to an all-true constant and isn't used by the
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output template:
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@smallexample
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(define_insn_and_rewrite "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(unspec:SI [(match_operand:PRED_ALL 1)
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(unspec:PRED_ALL
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[(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")
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(match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")]
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UNSPEC_WHILE_LO)]
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UNSPEC_PTEST_PTRUE)
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(const_int 0)))
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(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
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(unspec:PRED_ALL [(match_dup 2)
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(match_dup 3)]
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UNSPEC_WHILE_LO))]
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"TARGET_SVE"
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"whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3"
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;; Force the compiler to drop the unused predicate operand, so that we
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;; don't have an unnecessary PTRUE.
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"&& !CONSTANT_P (operands[1])"
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@{
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operands[1] = CONSTM1_RTX (<MODE>mode);
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@}
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)
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@end smallexample
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The splitter in this case simply replaces operand 1 with the constant
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value that it is known to have. The equivalent @code{define_insn_and_split}
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would be:
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@smallexample
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(define_insn_and_split "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(unspec:SI [(match_operand:PRED_ALL 1)
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(unspec:PRED_ALL
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[(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")
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(match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")]
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UNSPEC_WHILE_LO)]
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UNSPEC_PTEST_PTRUE)
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(const_int 0)))
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(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
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(unspec:PRED_ALL [(match_dup 2)
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(match_dup 3)]
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UNSPEC_WHILE_LO))]
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"TARGET_SVE"
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"whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3"
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;; Force the compiler to drop the unused predicate operand, so that we
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;; don't have an unnecessary PTRUE.
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"&& !CONSTANT_P (operands[1])"
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[(parallel
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(unspec:SI [(match_dup 1)
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(unspec:PRED_ALL [(match_dup 2)
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(match_dup 3)]
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UNSPEC_WHILE_LO)]
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UNSPEC_PTEST_PTRUE)
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(const_int 0)))
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(set (match_dup 0)
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(unspec:PRED_ALL [(match_dup 2)
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(match_dup 3)]
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UNSPEC_WHILE_LO))])]
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@{
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operands[1] = CONSTM1_RTX (<MODE>mode);
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@}
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)
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@end smallexample
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@end ifset
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@ifset INTERNALS
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@node Including Patterns
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@ -70,8 +70,8 @@ struct queue_elem
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rtx data;
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file_location loc;
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struct queue_elem *next;
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/* In a DEFINE_INSN that came from a DEFINE_INSN_AND_SPLIT, SPLIT
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points to the generated DEFINE_SPLIT. */
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/* In a DEFINE_INSN that came from a DEFINE_INSN_AND_SPLIT or
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DEFINE_INSN_AND_REWRITE, SPLIT points to the generated DEFINE_SPLIT. */
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struct queue_elem *split;
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};
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@ -485,6 +485,63 @@ remove_constraints (rtx part)
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}
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}
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/* Recursively replace MATCH_OPERANDs with MATCH_DUPs and MATCH_OPERATORs
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with MATCH_OP_DUPs in X. */
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static rtx
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replace_operands_with_dups (rtx x)
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{
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if (x == 0)
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return x;
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rtx newx;
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if (GET_CODE (x) == MATCH_OPERAND)
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{
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newx = rtx_alloc (MATCH_DUP);
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XINT (newx, 0) = XINT (x, 0);
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}
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else if (GET_CODE (x) == MATCH_OPERATOR)
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{
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newx = rtx_alloc (MATCH_OP_DUP);
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XINT (newx, 0) = XINT (x, 0);
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XVEC (newx, 1) = XVEC (x, 2);
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}
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else
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newx = shallow_copy_rtx (x);
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const char *format_ptr = GET_RTX_FORMAT (GET_CODE (x));
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for (int i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
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switch (*format_ptr++)
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{
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case 'e':
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case 'u':
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XEXP (newx, i) = replace_operands_with_dups (XEXP (x, i));
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break;
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case 'E':
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if (XVEC (x, i) != NULL)
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{
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XVEC (newx, i) = rtvec_alloc (XVECLEN (x, i));
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for (int j = 0; j < XVECLEN (x, i); j++)
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XVECEXP (newx, i, j)
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= replace_operands_with_dups (XVECEXP (x, i, j));
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}
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break;
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}
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return newx;
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}
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/* Convert matching pattern VEC from a DEFINE_INSN_AND_REWRITE into
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a sequence that should be generated by the splitter. */
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static rtvec
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gen_rewrite_sequence (rtvec vec)
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{
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rtvec new_vec = rtvec_alloc (1);
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rtx x = add_implicit_parallel (vec);
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RTVEC_ELT (new_vec, 0) = replace_operands_with_dups (x);
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return new_vec;
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}
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/* Process a top level rtx in some way, queuing as appropriate. */
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static void
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||||
|
|
@ -527,6 +584,7 @@ process_rtx (rtx desc, file_location loc)
|
|||
break;
|
||||
|
||||
case DEFINE_INSN_AND_SPLIT:
|
||||
case DEFINE_INSN_AND_REWRITE:
|
||||
{
|
||||
const char *split_cond;
|
||||
rtx split;
|
||||
|
|
@ -534,6 +592,7 @@ process_rtx (rtx desc, file_location loc)
|
|||
int i;
|
||||
struct queue_elem *insn_elem;
|
||||
struct queue_elem *split_elem;
|
||||
int split_code = (GET_CODE (desc) == DEFINE_INSN_AND_REWRITE ? 5 : 6);
|
||||
|
||||
/* Create a split with values from the insn_and_split. */
|
||||
split = rtx_alloc (DEFINE_SPLIT);
|
||||
|
|
@ -555,12 +614,17 @@ process_rtx (rtx desc, file_location loc)
|
|||
split_cond = rtx_reader_ptr->join_c_conditions (XSTR (desc, 2),
|
||||
split_cond + 2);
|
||||
}
|
||||
else if (GET_CODE (desc) == DEFINE_INSN_AND_REWRITE)
|
||||
error_at (loc, "the rewrite condition must start with `&&'");
|
||||
XSTR (split, 1) = split_cond;
|
||||
XVEC (split, 2) = XVEC (desc, 5);
|
||||
XSTR (split, 3) = XSTR (desc, 6);
|
||||
if (GET_CODE (desc) == DEFINE_INSN_AND_REWRITE)
|
||||
XVEC (split, 2) = gen_rewrite_sequence (XVEC (desc, 1));
|
||||
else
|
||||
XVEC (split, 2) = XVEC (desc, 5);
|
||||
XSTR (split, 3) = XSTR (desc, split_code);
|
||||
|
||||
/* Fix up the DEFINE_INSN. */
|
||||
attr = XVEC (desc, 7);
|
||||
attr = XVEC (desc, split_code + 1);
|
||||
PUT_CODE (desc, DEFINE_INSN);
|
||||
XVEC (desc, 4) = attr;
|
||||
|
||||
|
|
|
|||
|
|
@ -286,9 +286,11 @@ apply_subst_iterator (rtx rt, unsigned int, int value)
|
|||
return;
|
||||
gcc_assert (GET_CODE (rt) == DEFINE_INSN
|
||||
|| GET_CODE (rt) == DEFINE_INSN_AND_SPLIT
|
||||
|| GET_CODE (rt) == DEFINE_INSN_AND_REWRITE
|
||||
|| GET_CODE (rt) == DEFINE_EXPAND);
|
||||
|
||||
int attrs = GET_CODE (rt) == DEFINE_INSN_AND_SPLIT ? 7 : 4;
|
||||
int attrs = (GET_CODE (rt) == DEFINE_INSN_AND_SPLIT ? 7
|
||||
: GET_CODE (rt) == DEFINE_INSN_AND_REWRITE ? 6 : 4);
|
||||
attrs_vec = XVEC (rt, attrs);
|
||||
|
||||
/* If we've already added attribute 'current_iterator_name', then we
|
||||
|
|
@ -549,6 +551,7 @@ add_condition_to_rtx (rtx x, const char *extra)
|
|||
break;
|
||||
|
||||
case DEFINE_INSN_AND_SPLIT:
|
||||
case DEFINE_INSN_AND_REWRITE:
|
||||
XSTR (x, 2) = add_condition_to_string (XSTR (x, 2), extra);
|
||||
XSTR (x, 4) = add_condition_to_string (XSTR (x, 4), extra);
|
||||
break;
|
||||
|
|
@ -632,6 +635,7 @@ named_rtx_p (rtx x)
|
|||
case DEFINE_EXPAND:
|
||||
case DEFINE_INSN:
|
||||
case DEFINE_INSN_AND_SPLIT:
|
||||
case DEFINE_INSN_AND_REWRITE:
|
||||
return true;
|
||||
|
||||
default:
|
||||
|
|
@ -1837,8 +1841,8 @@ rtx_reader::read_rtx_operand (rtx return_rtx, int idx)
|
|||
break;
|
||||
}
|
||||
|
||||
/* The output template slot of a DEFINE_INSN,
|
||||
DEFINE_INSN_AND_SPLIT, or DEFINE_PEEPHOLE automatically
|
||||
/* The output template slot of a DEFINE_INSN, DEFINE_INSN_AND_SPLIT,
|
||||
DEFINE_INSN_AND_REWRITE or DEFINE_PEEPHOLE automatically
|
||||
gets a star inserted as its first character, if it is
|
||||
written with a brace block instead of a string constant. */
|
||||
star_if_braced = (format_ptr[idx] == 'T');
|
||||
|
|
@ -1855,7 +1859,8 @@ rtx_reader::read_rtx_operand (rtx return_rtx, int idx)
|
|||
if (*stringbuf == '\0'
|
||||
&& idx == 0
|
||||
&& (GET_CODE (return_rtx) == DEFINE_INSN
|
||||
|| GET_CODE (return_rtx) == DEFINE_INSN_AND_SPLIT))
|
||||
|| GET_CODE (return_rtx) == DEFINE_INSN_AND_SPLIT
|
||||
|| GET_CODE (return_rtx) == DEFINE_INSN_AND_REWRITE))
|
||||
{
|
||||
struct obstack *string_obstack = get_string_obstack ();
|
||||
char line_name[20];
|
||||
|
|
|
|||
|
|
@ -936,6 +936,12 @@ DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
|
|||
7: optionally, a vector of attributes for this insn. */
|
||||
DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
|
||||
|
||||
/* A form of define_insn_and_split in which the split insn pattern (operand 5)
|
||||
is determined automatically by replacing match_operands with match_dups
|
||||
and match_operators with match_op_dups. The operands are the same as
|
||||
define_insn_and_split but with operand 5 removed. */
|
||||
DEF_RTL_EXPR(DEFINE_INSN_AND_REWRITE, "define_insn_and_rewrite", "sEsTsSV", RTX_EXTRA)
|
||||
|
||||
/* Definition of an RTL peephole operation.
|
||||
Follows the same arguments as define_split. */
|
||||
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue