re PR middle-end/63155 (memory hog)
2018-10-05 Richard Biener <rguenther@suse.de> PR tree-optimization/63155 * tree-ssa-ccp.c (ccp_propagate::visit_phi): Avoid excess vertical space in dumpfiles. * tree-ssa-propagate.h (ssa_propagation_engine::process_ssa_edge_worklist): Remove. * tree-ssa-propagate.c (cfg_blocks_back): New global. (ssa_edge_worklist_back): Likewise. (curr_order): Likewise. (cfg_blocks_get): Remove abstraction. (cfg_blocks_add): Likewise. (cfg_blocks_empty_p): Likewise. (add_ssa_edge): Add to current or next worklist based on RPO index. (add_control_edge): Likewise. (ssa_propagation_engine::process_ssa_edge_worklist): Fold into ... (ssa_propagation_engine::ssa_propagate): ... here. Unify iteration from CFG and SSA edge worklist so we process everything in RPO order, prioritizing forward progress over iteration. (ssa_prop_init): Allocate new worklists, do not dump immediate uses. (ssa_prop_fini): Free new worklists. From-SVN: r264869
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Richard Biener
Richard Biener
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700adeb6fd
commit
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4 changed files with 106 additions and 81 deletions
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@ -1,3 +1,29 @@
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2018-10-05 Richard Biener <rguenther@suse.de>
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PR tree-optimization/63155
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* tree-ssa-ccp.c (ccp_propagate::visit_phi): Avoid excess
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vertical space in dumpfiles.
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* tree-ssa-propagate.h
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(ssa_propagation_engine::process_ssa_edge_worklist): Remove.
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* tree-ssa-propagate.c (cfg_blocks_back): New global.
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(ssa_edge_worklist_back): Likewise.
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(curr_order): Likewise.
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(cfg_blocks_get): Remove abstraction.
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(cfg_blocks_add): Likewise.
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(cfg_blocks_empty_p): Likewise.
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(add_ssa_edge): Add to current or next worklist based on
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RPO index.
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(add_control_edge): Likewise.
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(ssa_propagation_engine::process_ssa_edge_worklist): Fold
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into ...
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(ssa_propagation_engine::ssa_propagate): ... here. Unify
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iteration from CFG and SSA edge worklist so we process
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everything in RPO order, prioritizing forward progress
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over iteration.
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(ssa_prop_init): Allocate new worklists, do not dump
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immediate uses.
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(ssa_prop_fini): Free new worklists.
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2018-10-05 Richard Biener <rguenther@suse.de>
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* tree-core.h (tree_block::abstract_flag): Remove.
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@ -1119,7 +1119,7 @@ ccp_propagate::visit_phi (gphi *phi)
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if (dump_file && (dump_flags & TDF_DETAILS))
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{
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fprintf (dump_file,
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"\n Argument #%d (%d -> %d %sexecutable)\n",
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"\tArgument #%d (%d -> %d %sexecutable)\n",
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i, e->src->index, e->dest->index,
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(e->flags & EDGE_EXECUTABLE) ? "" : "not ");
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}
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@ -108,51 +108,26 @@
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[3] Advanced Compiler Design and Implementation,
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Steven Muchnick, Morgan Kaufmann, 1997, Section 12.6 */
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/* Worklist of control flow edge destinations. This contains
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/* Worklists of control flow edge destinations. This contains
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the CFG order number of the blocks so we can iterate in CFG
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order by visiting in bit-order. */
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order by visiting in bit-order. We use two worklists to
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first make forward progress before iterating. */
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static bitmap cfg_blocks;
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static bitmap cfg_blocks_back;
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static int *bb_to_cfg_order;
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static int *cfg_order_to_bb;
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/* Worklist of SSA edges which will need reexamination as their
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/* Worklists of SSA edges which will need reexamination as their
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definition has changed. SSA edges are def-use edges in the SSA
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web. For each D-U edge, we store the target statement or PHI node
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UID in a bitmap. UIDs order stmts in execution order. */
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UID in a bitmap. UIDs order stmts in execution order. We use
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two worklists to first make forward progress before iterating. */
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static bitmap ssa_edge_worklist;
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static bitmap ssa_edge_worklist_back;
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static vec<gimple *> uid_to_stmt;
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/* Return true if the block worklist empty. */
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static inline bool
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cfg_blocks_empty_p (void)
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{
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return bitmap_empty_p (cfg_blocks);
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}
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/* Add a basic block to the worklist. The block must not be the ENTRY
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or EXIT block. */
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static void
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cfg_blocks_add (basic_block bb)
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{
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gcc_assert (bb != ENTRY_BLOCK_PTR_FOR_FN (cfun)
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&& bb != EXIT_BLOCK_PTR_FOR_FN (cfun));
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bitmap_set_bit (cfg_blocks, bb_to_cfg_order[bb->index]);
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}
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/* Remove a block from the worklist. */
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static basic_block
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cfg_blocks_get (void)
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{
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gcc_assert (!cfg_blocks_empty_p ());
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int order_index = bitmap_first_set_bit (cfg_blocks);
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bitmap_clear_bit (cfg_blocks, order_index);
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return BASIC_BLOCK_FOR_FN (cfun, cfg_order_to_bb [order_index]);
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}
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/* Current RPO index in the iteration. */
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static int curr_order;
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/* We have just defined a new value for VAR. If IS_VARYING is true,
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@ -182,8 +157,15 @@ add_ssa_edge (tree var)
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& EDGE_EXECUTABLE))
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continue;
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if (prop_simulate_again_p (use_stmt)
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&& bitmap_set_bit (ssa_edge_worklist, gimple_uid (use_stmt)))
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if (!prop_simulate_again_p (use_stmt))
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continue;
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bitmap worklist;
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if (bb_to_cfg_order[gimple_bb (use_stmt)->index] < curr_order)
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worklist = ssa_edge_worklist_back;
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else
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worklist = ssa_edge_worklist;
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if (bitmap_set_bit (worklist, gimple_uid (use_stmt)))
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{
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uid_to_stmt[gimple_uid (use_stmt)] = use_stmt;
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if (dump_file && (dump_flags & TDF_DETAILS))
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@ -211,7 +193,11 @@ add_control_edge (edge e)
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e->flags |= EDGE_EXECUTABLE;
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cfg_blocks_add (bb);
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int bb_order = bb_to_cfg_order[bb->index];
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if (bb_order < curr_order)
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bitmap_set_bit (cfg_blocks_back, bb_order);
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else
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bitmap_set_bit (cfg_blocks, bb_order);
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if (dump_file && (dump_flags & TDF_DETAILS))
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fprintf (dump_file, "Adding destination of edge (%d -> %d) to worklist\n",
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@ -318,33 +304,6 @@ ssa_propagation_engine::simulate_stmt (gimple *stmt)
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}
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}
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/* Process an SSA edge worklist. WORKLIST is the SSA edge worklist to
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drain. This pops statements off the given WORKLIST and processes
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them until one statement was simulated or there are no more statements
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on WORKLIST. We take a pointer to WORKLIST because it may be reallocated
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when an SSA edge is added to it in simulate_stmt. Return true if a stmt
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was simulated. */
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void
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ssa_propagation_engine::process_ssa_edge_worklist (void)
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{
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/* Process the next entry from the worklist. */
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unsigned stmt_uid = bitmap_first_set_bit (ssa_edge_worklist);
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bitmap_clear_bit (ssa_edge_worklist, stmt_uid);
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gimple *stmt = uid_to_stmt[stmt_uid];
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/* We should not have stmts in not yet simulated BBs on the worklist. */
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gcc_assert (gimple_bb (stmt)->flags & BB_VISITED);
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if (dump_file && (dump_flags & TDF_DETAILS))
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{
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fprintf (dump_file, "\nSimulating statement: ");
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print_gimple_stmt (dump_file, stmt, 0, dump_flags);
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}
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simulate_stmt (stmt);
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}
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/* Simulate the execution of BLOCK. Evaluate the statement associated
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with each variable reference inside the block. */
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@ -422,6 +381,7 @@ ssa_prop_init (void)
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/* Worklists of SSA edges. */
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ssa_edge_worklist = BITMAP_ALLOC (NULL);
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ssa_edge_worklist_back = BITMAP_ALLOC (NULL);
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/* Worklist of basic-blocks. */
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bb_to_cfg_order = XNEWVEC (int, last_basic_block_for_fn (cfun) + 1);
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@ -431,9 +391,7 @@ ssa_prop_init (void)
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for (int i = 0; i < n; ++i)
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bb_to_cfg_order[cfg_order_to_bb[i]] = i;
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cfg_blocks = BITMAP_ALLOC (NULL);
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if (dump_file && (dump_flags & TDF_DETAILS))
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dump_immediate_uses (dump_file);
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cfg_blocks_back = BITMAP_ALLOC (NULL);
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/* Initially assume that every edge in the CFG is not executable.
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(including the edges coming out of the entry block). Mark blocks
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@ -479,9 +437,11 @@ static void
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ssa_prop_fini (void)
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{
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BITMAP_FREE (cfg_blocks);
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BITMAP_FREE (cfg_blocks_back);
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free (bb_to_cfg_order);
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free (cfg_order_to_bb);
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BITMAP_FREE (ssa_edge_worklist);
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BITMAP_FREE (ssa_edge_worklist_back);
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uid_to_stmt.release ();
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}
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@ -796,21 +756,62 @@ ssa_propagation_engine::ssa_propagate (void)
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{
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ssa_prop_init ();
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/* Iterate until the worklists are empty. */
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while (! cfg_blocks_empty_p ()
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|| ! bitmap_empty_p (ssa_edge_worklist))
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curr_order = 0;
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/* Iterate until the worklists are empty. We iterate both blocks
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and stmts in RPO order, using sets of two worklists to first
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complete the current iteration before iterating over backedges. */
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while (1)
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{
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/* First simulate whole blocks. */
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if (! cfg_blocks_empty_p ())
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int next_block_order = (bitmap_empty_p (cfg_blocks)
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? -1 : bitmap_first_set_bit (cfg_blocks));
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int next_stmt_uid = (bitmap_empty_p (ssa_edge_worklist)
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? -1 : bitmap_first_set_bit (ssa_edge_worklist));
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if (next_block_order == -1 && next_stmt_uid == -1)
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{
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/* Pull the next block to simulate off the worklist. */
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basic_block dest_block = cfg_blocks_get ();
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simulate_block (dest_block);
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if (bitmap_empty_p (cfg_blocks_back)
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&& bitmap_empty_p (ssa_edge_worklist_back))
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break;
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if (dump_file && (dump_flags & TDF_DETAILS))
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fprintf (dump_file, "Regular worklists empty, now processing "
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"backedge destinations\n");
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std::swap (cfg_blocks, cfg_blocks_back);
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std::swap (ssa_edge_worklist, ssa_edge_worklist_back);
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continue;
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}
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/* Then simulate from the SSA edge worklist. */
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process_ssa_edge_worklist ();
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int next_stmt_bb_order = -1;
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gimple *next_stmt = NULL;
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if (next_stmt_uid != -1)
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{
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next_stmt = uid_to_stmt[next_stmt_uid];
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next_stmt_bb_order = bb_to_cfg_order[gimple_bb (next_stmt)->index];
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}
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/* Pull the next block to simulate off the worklist if it comes first. */
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if (next_block_order != -1
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&& (next_stmt_bb_order == -1
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|| next_block_order <= next_stmt_bb_order))
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{
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curr_order = next_block_order;
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bitmap_clear_bit (cfg_blocks, next_block_order);
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basic_block bb
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= BASIC_BLOCK_FOR_FN (cfun, cfg_order_to_bb [next_block_order]);
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simulate_block (bb);
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}
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/* Else simulate from the SSA edge worklist. */
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else
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{
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curr_order = next_stmt_bb_order;
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bitmap_clear_bit (ssa_edge_worklist, next_stmt_uid);
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if (dump_file && (dump_flags & TDF_DETAILS))
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{
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fprintf (dump_file, "\nSimulating statement: ");
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print_gimple_stmt (dump_file, next_stmt, 0, dump_flags);
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}
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simulate_stmt (next_stmt);
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}
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}
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ssa_prop_fini ();
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@ -94,9 +94,7 @@ class ssa_propagation_engine
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private:
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/* Internal implementation details. */
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void simulate_stmt (gimple *stmt);
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void process_ssa_edge_worklist (void);
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void simulate_block (basic_block);
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};
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class substitute_and_fold_engine
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