[NDS32] Refine call and return patterns.
gcc/ * config/nds32/nds32-md-auxiliary.c (nds32_output_return, nds32_output_call, nds32_symbol_binds_local_p): New functions. * config/nds32/nds32-protos.h (nds32_output_call, nds32_output_return): Declare. * config/nds32/nds32.md: Refine all the call and return patterns. Co-Authored-By: Kito Cheng <kito.cheng@gmail.com> From-SVN: r259186
This commit is contained in:
Chung-Ju Wu
Chung-Ju Wu
parent
96975b1159
commit
f467067339
4 changed files with 211 additions and 53 deletions
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@ -1,3 +1,12 @@
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2018-04-06 Chung-Ju Wu <jasonwucj@gmail.com>
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Kito Cheng <kito.cheng@gmail.com>
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* config/nds32/nds32-md-auxiliary.c (nds32_output_return,
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nds32_output_call, nds32_symbol_binds_local_p): New functions.
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* config/nds32/nds32-protos.h (nds32_output_call,
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nds32_output_return): Declare.
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* config/nds32/nds32.md: Refine all the call and return patterns.
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2018-04-06 Jakub Jelinek <jakub@redhat.com>
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PR debug/85252
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@ -1938,6 +1938,48 @@ nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
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return "";
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}
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/* Function to output return operation. */
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const char *
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nds32_output_return (void)
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{
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/* A string pattern for output_asm_insn(). */
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char pattern[100];
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/* The operands array which will be used in output_asm_insn(). */
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rtx operands[2];
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/* For stack v3pop:
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operands[0]: Re
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operands[1]: imm8u */
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int re_callee_saved = cfun->machine->callee_saved_last_gpr_regno;
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int sp_adjust;
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/* Set operands[0]. */
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operands[0] = gen_rtx_REG (SImode, re_callee_saved);
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/* Check if we can generate 'pop25 Re,imm8u',
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otherwise, generate 'pop25 Re,0'.
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We have to consider alloca issue as well.
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If the function does call alloca(), the stack pointer is not fixed.
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In that case, we cannot use 'pop25 Re,imm8u' directly.
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We have to caculate stack pointer from frame pointer
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and then use 'pop25 Re,0'. */
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sp_adjust = cfun->machine->local_size
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+ cfun->machine->out_args_size
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+ cfun->machine->callee_saved_area_gpr_padding_bytes
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+ cfun->machine->callee_saved_fpr_regs_size;
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if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
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&& NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
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&& !cfun->calls_alloca)
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operands[1] = GEN_INT (sp_adjust);
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else
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operands[1] = GEN_INT (0);
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/* Create assembly code pattern. */
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snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
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/* We use output_asm_insn() to output assembly code by ourself. */
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output_asm_insn (pattern, operands);
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return "";
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}
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/* Function to generate PC relative jump table.
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Refer to nds32.md for more details.
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@ -2681,6 +2723,56 @@ nds32_output_cbranchsi4_greater_less_zero (rtx_insn *insn, rtx *operands)
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return "";
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}
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/* Return true if SYMBOL_REF X binds locally. */
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static bool
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nds32_symbol_binds_local_p (const_rtx x)
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{
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return (SYMBOL_REF_DECL (x)
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? targetm.binds_local_p (SYMBOL_REF_DECL (x))
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: SYMBOL_REF_LOCAL_P (x));
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}
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const char *
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nds32_output_call (rtx insn, rtx *operands, rtx symbol, const char *long_call,
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const char *call, bool align_p)
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{
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char pattern[100];
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bool noreturn_p;
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if (GET_CODE (symbol) == CONST)
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{
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symbol= XEXP (symbol, 0);
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if (GET_CODE (symbol) == PLUS)
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symbol = XEXP (symbol, 0);
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}
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gcc_assert (GET_CODE (symbol) == SYMBOL_REF
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|| REG_P (symbol));
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if (nds32_long_call_p (symbol))
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strcpy (pattern, long_call);
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else
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strcpy (pattern, call);
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if (align_p)
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strcat (pattern, "\n\t.align 2");
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noreturn_p = find_reg_note (insn, REG_NORETURN, NULL_RTX) != NULL_RTX;
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if (noreturn_p)
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{
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if (TARGET_16_BIT)
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strcat (pattern, "\n\tnop16");
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else
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strcat (pattern, "\n\tnop");
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}
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output_asm_insn (pattern, operands);
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return "";
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}
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/* Spilt a doubleword instrucion to two single word instructions. */
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void
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nds32_spilt_doubleword (rtx *operands, bool load_p)
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@ -172,11 +172,15 @@ extern const char *nds32_output_cbranchsi4_equality_reg_or_const_int (rtx_insn *
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rtx *);
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extern const char *nds32_output_cbranchsi4_greater_less_zero (rtx_insn *, rtx *);
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extern const char *nds32_output_call (rtx, rtx *, rtx,
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const char *, const char *, bool);
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/* Auxiliary functions to output stack push/pop instruction. */
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extern const char *nds32_output_stack_push (rtx);
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extern const char *nds32_output_stack_pop (rtx);
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extern const char *nds32_output_return (void);
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/* Auxiliary functions to split double word RTX pattern. */
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@ -1419,36 +1419,41 @@
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""
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)
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(define_insn "*call_register"
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[(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
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(match_operand 1))
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(clobber (reg:SI LP_REGNUM))
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(clobber (reg:SI TA_REGNUM))])]
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""
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"@
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jral5\t%0
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jral\t%0"
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[(set_attr "type" "branch,branch")
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(set_attr "length" " 2, 4")])
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(define_insn "*call_immediate"
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[(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
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(define_insn "call_internal"
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[(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i"))
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(match_operand 1))
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(clobber (reg:SI LP_REGNUM))
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(clobber (reg:SI TA_REGNUM))])]
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""
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{
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if (TARGET_CMODEL_LARGE)
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return "bal\t%0";
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else
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return "jal\t%0";
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switch (which_alternative)
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{
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case 0:
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if (TARGET_16_BIT)
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return "jral5\t%0";
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else
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return "jral\t%0";
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case 1:
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return nds32_output_call (insn, operands, operands[0],
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"bal\t%0", "jal\t%0", false);
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "branch")
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(set (attr "length")
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(if_then_else (match_test "TARGET_CMODEL_LARGE")
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(const_int 12)
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(const_int 4)))])
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[(set_attr "enabled" "yes")
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(set_attr "type" "branch")
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(set_attr_alternative "length"
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[
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;; Alternative 0
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(if_then_else (match_test "TARGET_16_BIT")
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(const_int 2)
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(const_int 4))
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;; Alternative 1
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(if_then_else (match_test "nds32_long_call_p (operands[0])")
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(const_int 12)
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(const_int 4))
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])]
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)
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;; Subroutine call instruction returning a value.
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;; operands[0]: It is the hard regiser in which the value is returned.
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@ -1462,42 +1467,71 @@
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(match_operand 2)))
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(clobber (reg:SI LP_REGNUM))
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(clobber (reg:SI TA_REGNUM))])]
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""
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""
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)
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"")
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(define_insn "*call_value_register"
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(define_insn "call_value_internal"
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[(parallel [(set (match_operand 0)
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(call (mem (match_operand:SI 1 "register_operand" "r, r"))
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(call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i"))
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(match_operand 2)))
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(clobber (reg:SI LP_REGNUM))
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(clobber (reg:SI TA_REGNUM))])]
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""
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"@
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jral5\t%1
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jral\t%1"
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[(set_attr "type" "branch,branch")
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(set_attr "length" " 2, 4")])
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{
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switch (which_alternative)
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{
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case 0:
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if (TARGET_16_BIT)
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return "jral5\t%1";
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else
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return "jral\t%1";
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case 1:
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return nds32_output_call (insn, operands, operands[1],
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"bal\t%1", "jal\t%1", false);
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "enabled" "yes")
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(set_attr "type" "branch")
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(set_attr_alternative "length"
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[
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;; Alternative 0
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(if_then_else (match_test "TARGET_16_BIT")
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(const_int 2)
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(const_int 4))
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;; Alternative 1
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(if_then_else (match_test "nds32_long_call_p (operands[1])")
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(const_int 12)
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(const_int 4))
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])]
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)
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(define_insn "*call_value_immediate"
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[(parallel [(set (match_operand 0)
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(call (mem (match_operand:SI 1 "immediate_operand" "i"))
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(match_operand 2)))
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(clobber (reg:SI LP_REGNUM))
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(clobber (reg:SI TA_REGNUM))])]
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;; Call subroutine returning any type.
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(define_expand "untyped_call"
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[(parallel [(call (match_operand 0 "" "")
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(const_int 0))
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(match_operand 1 "" "")
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(match_operand 2 "" "")])]
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""
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{
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if (TARGET_CMODEL_LARGE)
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return "bal\t%1";
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else
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return "jal\t%1";
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}
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[(set_attr "type" "branch")
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(set (attr "length")
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(if_then_else (match_test "TARGET_CMODEL_LARGE")
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(const_int 12)
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(const_int 4)))])
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int i;
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emit_call_insn (gen_call (operands[0], const0_rtx));
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for (i = 0; i < XVECLEN (operands[2], 0); i++)
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{
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rtx set = XVECEXP (operands[2], 0, i);
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emit_move_insn (SET_DEST (set), SET_SRC (set));
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}
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/* The optimizer does not know that the call sets the function value
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registers we stored in the result block. We avoid problems by
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claiming that all hard registers are used and clobbered at this
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point. */
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emit_insn (gen_blockage ());
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DONE;
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})
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;; ----------------------------------------------------------------------------
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@ -1715,10 +1749,18 @@
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;; Use this pattern to expand a return instruction
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;; with simple_return rtx if no epilogue is required.
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(define_expand "return"
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[(simple_return)]
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[(parallel [(return)
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(clobber (reg:SI FP_REGNUM))])]
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"nds32_can_use_return_insn ()"
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""
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)
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{
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/* Emit as the simple return. */
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if (cfun->machine->naked_p
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&& (cfun->machine->va_args_size == 0))
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{
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emit_jump_insn (gen_return_internal ());
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DONE;
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}
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})
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;; This pattern is expanded only by the shrink-wrapping optimization
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;; on paths where the function prologue has not been executed.
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@ -1728,6 +1770,17 @@
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""
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)
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(define_insn "*nds32_return"
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[(parallel [(return)
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(clobber (reg:SI FP_REGNUM))])]
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""
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{
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return nds32_output_return ();
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}
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[(set_attr "type" "branch")
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(set_attr "enabled" "yes")
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(set_attr "length" "4")])
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(define_insn "return_internal"
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[(simple_return)]
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""
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