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invoke.texi: Document -mam34 and -mtune options.

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* doc/invoke.texi: Document -mam34 and -mtune options.
        * config/mn10300/mn10300.c (mn10300_tune_string): New variable.
        (mn10300_tune_cpu): New variable.
        (mn10300_handle_option): Handle -mam34 and -mtune options.
        (mn10300_option_override): Convert tune string into tune cpu
        variable.
        (mn10300_legitimate_constant_p): Delete unused local variable.
        (is_load_insn): New function.
        (is_store_insn): New function.
        (mn10300_adjust_schedule_cost): New function.
        (TARGET_SCHED_ADJUST_COST): Define.
        * config/mn10300/mn10300.opt (mam34): New option.
        (mtune): New option.
        * config/mn10300/mn10300.h (TARGET_CPU_CPP_BUILTINS): Add AM34
        support.
        (enum processor_type): Add AM34.
        (TARGET_AM34): Define.
        * config/mn10300/mn10300.md (attr cpu): Add am34.
        Add pipeline description.
        (movqi, movhi, movsi, movsf, movdf, movdi): Fix predicates. Remove unneeded
        alternatives.  Add timing attribute.
        (pop_pic_reg, am33_addsi3, mn10300_addsi3, am33_subsi3,
        mn10300_subsi3, mulsidi3, umulsidi3, am33_mulsi3,
        mn10300_mulsi3, udivmodsi4_am33, divmodsi4, am33_andsi3,
        mn10300_andsi3, am33_iorsi3, mn10300_iorsi3, am33_xorsi3,
        mn10300_xorsi3, byte_clear, byte_set, bit_clear1, bit_clear2,
        bit_set, am33_iorqi3, mn10300_iorqi3, test_byte_bitfield,
        bit_test, subreg_bit_test, cmpsi, am33_cmpsf, am33_subsi3,
        float_conditional_branch, jump, indirect_jump, tablejump,
        call_internal, call_value_internal, zero_extendqisi2_am33,
        zero_extendqisi2_mn10300, zero_extendhisi2_am33,
        zero_extendhisi2_mn10300, extendqisi2_am33, extendqisi2_mn10300,
        extendhisi2_am33, extendhisi2_mn10300, am33_ashlsi3,
        mn10300_ashlsi3, am33_lshrsi3, mn10300_lshrsi3, am33_ashrisi3,
        mn10300_ashrsi3, abssf2_am33_2, negsf2_am33_2, rsqrtsf2,
        addsf3_internal, subsf3_internal, mulsf3_internal, divsf3,
        fmaddsf4, fmsubsf4, fnmaddsf4, fnmsubsf4, return_internal,
        return_internal_regs, store_movm, return, call_next_insn):
        Add timing attribute.
        (am33_subsi3): Add missing clobber of CC_REG.
        (am33_andsi3, mn10300_andsi3): Fix compile time warnings.
        (udivmodsi4, udivmodsi4_insn, divmodsi4, test_byte_bitfield,
        subreg_bit_test, zero_extendqisi2, zero_extendhisi2,
        extendqisi2): Fix predicates.
        (call_internal, call_internal_value): Separate alternatives.
        * config/mn10300/t-mn10300: Add AM34 multilib.

From-SVN: r166058
This commit is contained in:
Nick Clifton 2010-10-29 08:53:47 +00:00 • committed by Nick Clifton
parent 8a575d5a19
commit f3f637378c
7 changed files with 1199 additions and 630 deletions
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49
gcc/ChangeLog
View file

@ -1,3 +1,52 @@
2010-10-29 Nick Clifton<nickc@redhat.com>
* doc/invoke.texi: Document -mam34 and -mtune options.
* config/mn10300/mn10300.c (mn10300_tune_string): New variable.
(mn10300_tune_cpu): New variable.
(mn10300_handle_option): Handle -mam34 and -mtune options.
(mn10300_option_override): Convert tune string into tune cpu
variable.
(mn10300_legitimate_constant_p): Delete unused local variable.
(is_load_insn): New function.
(is_store_insn): New function.
(mn10300_adjust_schedule_cost): New function.
(TARGET_SCHED_ADJUST_COST): Define.
* config/mn10300/mn10300.opt (mam34): New option.
(mtune): New option.
* config/mn10300/mn10300.h (TARGET_CPU_CPP_BUILTINS): Add AM34
support.
(enum processor_type): Add AM34.
(TARGET_AM34): Define.
* config/mn10300/mn10300.md (attr cpu): Add am34.
Add pipeline description.
(movqi, movhi, movsi, movsf, movdf, movdi): Fix predicates. Remove unneeded
alternatives. Add timing attribute.
(pop_pic_reg, am33_addsi3, mn10300_addsi3, am33_subsi3,
mn10300_subsi3, mulsidi3, umulsidi3, am33_mulsi3,
mn10300_mulsi3, udivmodsi4_am33, divmodsi4, am33_andsi3,
mn10300_andsi3, am33_iorsi3, mn10300_iorsi3, am33_xorsi3,
mn10300_xorsi3, byte_clear, byte_set, bit_clear1, bit_clear2,
bit_set, am33_iorqi3, mn10300_iorqi3, test_byte_bitfield,
bit_test, subreg_bit_test, cmpsi, am33_cmpsf, am33_subsi3,
float_conditional_branch, jump, indirect_jump, tablejump,
call_internal, call_value_internal, zero_extendqisi2_am33,
zero_extendqisi2_mn10300, zero_extendhisi2_am33,
zero_extendhisi2_mn10300, extendqisi2_am33, extendqisi2_mn10300,
extendhisi2_am33, extendhisi2_mn10300, am33_ashlsi3,
mn10300_ashlsi3, am33_lshrsi3, mn10300_lshrsi3, am33_ashrisi3,
mn10300_ashrsi3, abssf2_am33_2, negsf2_am33_2, rsqrtsf2,
addsf3_internal, subsf3_internal, mulsf3_internal, divsf3,
fmaddsf4, fmsubsf4, fnmaddsf4, fnmsubsf4, return_internal,
return_internal_regs, store_movm, return, call_next_insn):
Add timing attribute.
(am33_subsi3): Add missing clobber of CC_REG.
(am33_andsi3, mn10300_andsi3): Fix compile time warnings.
(udivmodsi4, udivmodsi4_insn, divmodsi4, test_byte_bitfield,
subreg_bit_test, zero_extendqisi2, zero_extendhisi2,
extendqisi2): Fix predicates.
(call_internal, call_internal_value): Separate alternatives.
* config/mn10300/t-mn10300: Add AM34 multilib.
2010-10-29 Paolo Bonzini <bonzini@gnu.org>
* config/sh/sh.c (sh_promote_function_mode): Use

154
gcc/config/mn10300/mn10300.c
View file

@ -58,6 +58,12 @@ int mn10300_protect_label;
/* The selected processor. */
enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
/* Processor type to select for tuning. */
static const char * mn10300_tune_string = NULL;
/* Selected processor type for tuning. */
enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
/* The size of the callee register save area. Right now we save everything
on entry since it costs us nothing in code size. It does cost us from a
speed standpoint, so we want to optimize this sooner or later. */
@ -91,11 +97,21 @@ mn10300_handle_option (size_t code,
case OPT_mam33:
mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
return true;
case OPT_mam33_2:
mn10300_processor = (value
? PROCESSOR_AM33_2
: MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
return true;
case OPT_mam34:
mn10300_processor = (value ? PROCESSOR_AM34 : PROCESSOR_DEFAULT);
return true;
case OPT_mtune_:
mn10300_tune_string = arg;
return true;
default:
return true;
}
@ -108,6 +124,27 @@ mn10300_option_override (void)
{
if (TARGET_AM33)
target_flags &= ~MASK_MULT_BUG;
else
{
/* Disable scheduling for the MN10300 as we do
not have timing information available for it. */
flag_schedule_insns = 0;
flag_schedule_insns_after_reload = 0;
}
if (mn10300_tune_string)
{
if (strcasecmp (mn10300_tune_string, "mn10300") == 0)
mn10300_tune_cpu = PROCESSOR_MN10300;
else if (strcasecmp (mn10300_tune_string, "am33") == 0)
mn10300_tune_cpu = PROCESSOR_AM33;
else if (strcasecmp (mn10300_tune_string, "am33-2") == 0)
mn10300_tune_cpu = PROCESSOR_AM33_2;
else if (strcasecmp (mn10300_tune_string, "am34") == 0)
mn10300_tune_cpu = PROCESSOR_AM34;
else
error ("-mtune= expects mn10300, am33, am33-2, or am34");
}
}
static void
@ -370,7 +407,7 @@ mn10300_print_operand (FILE *file, rtx x, int code)
case 'A':
fputc ('(', file);
if (REG_P ((XEXP (x, 0))))
if (REG_P (XEXP (x, 0)))
output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
else
output_address (XEXP (x, 0));
@ -392,7 +429,7 @@ mn10300_print_operand (FILE *file, rtx x, int code)
shift count as an error. So we mask off the high bits
of the immediate here. */
case 'S':
if (CONST_INT_P ((x)))
if (CONST_INT_P (x))
{
fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
break;
@ -1250,8 +1287,8 @@ mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
/* Memory loads less than a full word wide can't have an
address or stack pointer destination. They must use
a data register as an intermediate register. */
if ((MEM_P ((in))
|| (REG_P ((inner))
if ((MEM_P (in)
|| (REG_P (inner)
&& REGNO (inner) >= FIRST_PSEUDO_REGISTER))
&& (mode == QImode || mode == HImode)
&& (rclass == ADDRESS_REGS || rclass == SP_REGS
@ -1281,13 +1318,13 @@ mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
{
/* We can't load directly into an FP register from a
constant address. */
if (MEM_P ((in))
if (MEM_P (in)
&& CONSTANT_ADDRESS_P (XEXP (in, 0)))
return DATA_OR_EXTENDED_REGS;
/* Handle case were a pseudo may not get a hard register
but has an equivalent memory location defined. */
if (REG_P ((inner))
if (REG_P (inner)
&& REGNO (inner) >= FIRST_PSEUDO_REGISTER
&& reg_equiv_mem [REGNO (inner)]
&& CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
@ -1696,7 +1733,7 @@ mn10300_symbolic_operand (rtx op,
op = XEXP (op, 0);
return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
&& CONST_INT_P ((XEXP (op, 1))));
&& CONST_INT_P (XEXP (op, 1)));
default:
return 0;
}
@ -1870,7 +1907,7 @@ mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
if (base != 0 && index != 0)
{
if (CONST_INT_P ((index)))
if (CONST_INT_P (index))
return TRUE;
if (GET_CODE (index) == CONST
&& GET_CODE (XEXP (index, 0)) != PLUS
@ -1907,7 +1944,6 @@ mn10300_legitimate_constant_p (rtx x)
/* Only some unspecs are valid as "constants". */
if (GET_CODE (x) == UNSPEC)
{
rtx sym = XVECEXP (x, 0, 0);
switch (XINT (x, 1))
{
case UNSPEC_INT_LABEL:
@ -2070,7 +2106,7 @@ mn10300_wide_const_load_uses_clr (rtx operands[2])
{
long val[2] = {0, 0};
if (! REG_P (operands[0])
if ((! REG_P (operands[0]))
|| REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
return false;
@ -2272,6 +2308,101 @@ mn10300_select_cc_mode (rtx x)
{
return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode;
}
static inline bool
is_load_insn (rtx insn)
{
if (GET_CODE (PATTERN (insn)) != SET)
return false;
return MEM_P (SET_SRC (PATTERN (insn)));
}
static inline bool
is_store_insn (rtx insn)
{
if (GET_CODE (PATTERN (insn)) != SET)
return false;
return MEM_P (SET_DEST (PATTERN (insn)));
}
/* Update scheduling costs for situations that cannot be
described using the attributes and DFA machinery.
DEP is the insn being scheduled.
INSN is the previous insn.
COST is the current cycle cost for DEP. */
static int
mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
{
int timings = get_attr_timings (insn);
if (!TARGET_AM33)
return 1;
if (GET_CODE (insn) == PARALLEL)
insn = XVECEXP (insn, 0, 0);
if (GET_CODE (dep) == PARALLEL)
dep = XVECEXP (dep, 0, 0);
/* For the AM34 a load instruction that follows a
store instruction incurs an extra cycle of delay. */
if (mn10300_tune_cpu == PROCESSOR_AM34
&& is_load_insn (dep)
&& is_store_insn (insn))
cost += 1;
/* For the AM34 a non-store, non-branch FPU insn that follows
another FPU insn incurs a one cycle throughput increase. */
else if (mn10300_tune_cpu == PROCESSOR_AM34
&& ! is_store_insn (insn)
&& ! JUMP_P (insn)
&& GET_CODE (PATTERN (dep)) == SET
&& GET_CODE (PATTERN (insn)) == SET
&& GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT
&& GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
cost += 1;
/* Resolve the conflict described in section 1-7-4 of
Chapter 3 of the MN103E Series Instruction Manual
where it says:
"When the preceeding instruction is a CPU load or
store instruction, a following FPU instruction
cannot be executed until the CPU completes the
latency period even though there are no register
or flag dependencies between them." */
/* Only the AM33-2 (and later) CPUs have FPU instructions. */
if (! TARGET_AM33_2)
return cost;
/* If a data dependence already exists then the cost is correct. */
if (REG_NOTE_KIND (link) == 0)
return cost;
/* Check that the instruction about to scheduled is an FPU instruction. */
if (GET_CODE (PATTERN (dep)) != SET)
return cost;
if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT)
return cost;
/* Now check to see if the previous instruction is a load or store. */
if (! is_load_insn (insn) && ! is_store_insn (insn))
return cost;
/* XXX: Verify: The text of 1-7-4 implies that the restriction
only applies when an INTEGER load/store preceeds an FPU
instruction, but is this true ? For now we assume that it is. */
if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
return cost;
/* Extract the latency value from the timings attribute. */
return timings < 100 ? (timings % 10) : (timings % 100);
}
/* Initialize the GCC target structure. */
@ -2347,4 +2478,7 @@ mn10300_select_cc_mode (rtx x)
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
struct gcc_target targetm = TARGET_INITIALIZER;

20
gcc/config/mn10300/mn10300.h
View file

@ -38,7 +38,12 @@
builtin_assert ("cpu=mn10300"); \
builtin_assert ("machine=mn10300"); \
\
if (TARGET_AM33_2) \
if (TARGET_AM34) \
{ \
builtin_define ("__AM33__=4"); \
builtin_define ("__AM34__"); \
} \
else if (TARGET_AM33_2) \
{ \
builtin_define ("__AM33__=2"); \
builtin_define ("__AM33_2__"); \
@ -54,13 +59,16 @@ enum processor_type
{
PROCESSOR_MN10300,
PROCESSOR_AM33,
PROCESSOR_AM33_2
PROCESSOR_AM33_2,
PROCESSOR_AM34
};
extern enum processor_type mn10300_processor;
extern enum processor_type mn10300_tune_cpu;
#define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33)
#define TARGET_AM33_2 (mn10300_processor == PROCESSOR_AM33_2)
#define TARGET_AM33_2 (mn10300_processor >= PROCESSOR_AM33_2)
#define TARGET_AM34 (mn10300_processor >= PROCESSOR_AM34)
#ifndef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_MN10300
@ -274,7 +282,7 @@ enum reg_class
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
#define REG_CLASS_NAMES \
{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
"SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
"EXTENDED_REGS", \
@ -289,7 +297,7 @@ enum reg_class
of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \
{ { 0, 0 }, /* No regs */ \
{ { 0, 0 }, /* No regs */ \
{ 0x0000000f, 0 }, /* DATA_REGS */ \
{ 0x000001f0, 0 }, /* ADDRESS_REGS */ \
{ 0x00000200, 0 }, /* SP_REGS */ \
@ -304,7 +312,7 @@ enum reg_class
{ 0x03fc0000, 0 }, /* FP_ACC_REGS */ \
{ 0x00000000, 0x80000 },/* CC_REGS */ \
{ 0x0003fdff, 0 }, /* GENERAL_REGS */ \
{ 0xffffffff, 0xfffff } /* ALL_REGS */ \
{ 0xffffffff, 0xfffff } /* ALL_REGS */ \
}
/* The following macro defines cover classes for Integrated Register

1573
gcc/config/mn10300/mn10300.md
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File diff suppressed because it is too large Load diff

10
gcc/config/mn10300/mn10300.opt
View file

@ -1,6 +1,6 @@
; Options for the Matsushita MN10300 port of the compiler.
; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
@ -26,6 +26,14 @@ mam33-2
Target
Target the AM33/2.0 processor
mam34
Target Report
Target the AM34 processor
mtune=
Target RejectNegative Joined
Tune code for the given processor
mmult-bug
Target Report Mask(MULT_BUG)
Work around hardware multiply bug

4
gcc/config/mn10300/t-mn10300
View file

@ -29,8 +29,8 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
MULTILIB_OPTIONS = mam33/mam33-2
MULTILIB_DIRNAMES = am33 am33-2
MULTILIB_OPTIONS = mam33/mam33-2/mam34
MULTILIB_DIRNAMES = am33 am33-2 am34
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib

19
gcc/doc/invoke.texi
View file

@ -734,8 +734,8 @@ Objective-C and Objective-C++ Dialects}.
@emph{MN10300 Options}
@gccoptlist{-mmult-bug -mno-mult-bug @gol
-mam33 -mno-am33 @gol
-mam33-2 -mno-am33-2 @gol
-mno-am33 -mam33 -mam33-2 -mam34 @gol
-mtune=@var{cpu-type} @gol
-mreturn-pointer-on-d0 @gol
-mno-crt0 -mrelax}
@ -14915,6 +14915,21 @@ Generate code which uses features specific to the AM33 processor.
Do not generate code which uses features specific to the AM33 processor. This
is the default.
@item -mam33-2
@opindex mam33-2
Generate code which uses features specific to the AM33/2.0 processor.
@item -mam34
@opindex mam34
Generate code which uses features specific to the AM34 processor.
@item -mtune=@var{cpu-type}
@opindex mtune
Use the timing characteristics of the indicated CPU type when
scheduling instructions. This does not change the targeted processor
type. The CPU type must be one of @samp{mn10300}, @samp{am33},
@samp{am33-2} or @samp{am34}.
@item -mreturn-pointer-on-d0
@opindex mreturn-pointer-on-d0
When generating a function which returns a pointer, return the pointer