S/390: Add patterns for r<nox>sbg instructions.
gcc/ChangeLog:
2016-05-03 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/s390.md ("*r<noxa>sbg_<mode>_sll")
("*r<noxa>sbg_<mode>_srl"): New define_insns.
("*r<noxa>sbg_<mode>_srl_bitmask"): Rename by adding "_bitmask".
("*r<noxa>sbg_<mode>_sll_bitmask"): Likewise.
gcc/testsuite/ChangeLog:
2016-05-03 Dominik Vogt <vogt@linux.vnet.ibm.com>
* gcc.target/s390/md/rXsbg_mode_sXl.c: New test.
* gcc.target/s390/s390.exp (check_effective_target_z10_instructions):
Procedure to check for z10 instruction set.
From-SVN: r235822
This commit is contained in:
Dominik Vogt
Andreas Krebbel
parent
1e26cec1ff
commit
f3d9004571
5 changed files with 207 additions and 2 deletions
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@ -1,3 +1,10 @@
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2016-05-03 Dominik Vogt <vogt@linux.vnet.ibm.com>
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* config/s390/s390.md ("*r<noxa>sbg_<mode>_sll")
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("*r<noxa>sbg_<mode>_srl"): New define_insns.
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("*r<noxa>sbg_<mode>_srl_bitmask"): Rename by adding "_bitmask".
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("*r<noxa>sbg_<mode>_sll_bitmask"): Likewise.
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2016-05-03 Alan Modra <amodra@gmail.com>
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* config/rs6000/rs6000.c (rs6000_savres_strategy): Correct condition
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@ -3989,7 +3989,7 @@
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"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
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[(set_attr "op_type" "RIE")])
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(define_insn "*r<noxa>sbg_<mode>_srl"
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(define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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(and:GPR
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@ -4005,7 +4005,7 @@
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"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
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[(set_attr "op_type" "RIE")])
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(define_insn "*r<noxa>sbg_<mode>_sll"
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(define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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(and:GPR
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@ -4021,6 +4021,36 @@
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"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
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[(set_attr "op_type" "RIE")])
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;; unsigned {int,long} a, b
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;; a = a | (b << const_int)
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;; a = a ^ (b << const_int)
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(define_insn "*r<noxa>sbg_<mode>_sll"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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(ashift:GPR
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(match_operand:GPR 1 "nonimmediate_operand" "d")
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(match_operand:GPR 2 "nonzero_shift_count_operand" ""))
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(match_operand:GPR 3 "nonimmediate_operand" "0")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10"
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"r<noxa>sbg\t%0,%1,64-<bitsize>,63-%2,%2"
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[(set_attr "op_type" "RIE")])
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;; unsigned {int,long} a, b
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;; a = a | (b >> const_int)
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;; a = a ^ (b >> const_int)
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(define_insn "*r<noxa>sbg_<mode>_srl"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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(lshiftrt:GPR
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(match_operand:GPR 1 "nonimmediate_operand" "d")
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(match_operand:GPR 2 "nonzero_shift_count_operand" ""))
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(match_operand:GPR 3 "nonimmediate_operand" "0")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10"
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"r<noxa>sbg\t%0,%1,64-<bitsize>+%2,63,64-%2"
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[(set_attr "op_type" "RIE")])
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;; These two are generated by combine for s.bf &= val.
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;; ??? For bitfields smaller than 32-bits, we wind up with SImode
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;; shifts and ands, which results in some truly awful patterns
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@ -1,3 +1,9 @@
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2016-05-03 Dominik Vogt <vogt@linux.vnet.ibm.com>
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* gcc.target/s390/md/rXsbg_mode_sXl.c: New test.
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* gcc.target/s390/s390.exp (check_effective_target_z10_instructions):
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Procedure to check for z10 instruction set.
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2016-05-03 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.dg/ipa/inline-8.c: Require c99_runtime.
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151
gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
Normal file
151
gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
Normal file
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@ -0,0 +1,151 @@
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/* Machine description pattern tests. */
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/*
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{ dg-options "-mzarch -save-temps" }
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Note that dejagnu-1.5.1 has a bug so that the action from the second dg-do
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always wins, even if the condition is false. If this test is run on hardware
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older than z10 with a buggy dejagnu release, the execution part will fail.
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{ dg-do assemble { target { ! z10_instructions } } }
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{ dg-do run { target { z10_instructions } } }
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Skip test if -O0, -march=z900, -march=z9-109 or -march=z9-ec is present on
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the command line:
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{ dg-skip-if "" { *-*-* } { "-march=z9*" "-O0" } { "" } }
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Skip test if the -O or the -march= option is missing from the command line
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because it's difficult to detect the default:
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{ dg-skip-if "" { *-*-* } { "*" } { "-O*" } }
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{ dg-skip-if "" { *-*-* } { "*" } { "-march=*" } }
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*/
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__attribute__ ((noinline)) unsigned int
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si_sll (unsigned int x)
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{
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return (x << 1);
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}
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__attribute__ ((noinline)) unsigned int
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si_srl (unsigned int x)
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{
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return (x >> 2);
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}
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__attribute__ ((noinline)) unsigned int
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rosbg_si_sll (unsigned int a, unsigned int b)
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{
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return a | (b << 1);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned int
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rosbg_si_srl (unsigned int a, unsigned int b)
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{
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return a | (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */
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__attribute__ ((noinline)) unsigned int
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rxsbg_si_sll (unsigned int a, unsigned int b)
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{
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return a ^ (b << 1);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned int
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rxsbg_si_srl (unsigned int a, unsigned int b)
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{
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return a ^ (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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di_sll (unsigned long long x)
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{
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return (x << 1);
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}
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__attribute__ ((noinline)) unsigned long long
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di_srl (unsigned long long x)
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{
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return (x >> 2);
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}
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__attribute__ ((noinline)) unsigned long long
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rosbg_di_sll (unsigned long long a, unsigned long long b)
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{
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return a | (b << 1);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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rosbg_di_srl (unsigned long long a, unsigned long long b)
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{
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return a | (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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rxsbg_di_sll (unsigned long long a, unsigned long long b)
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{
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return a ^ (b << 1);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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rxsbg_di_srl (unsigned long long a, unsigned long long b)
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{
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return a ^ (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */
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int
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main (void)
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{
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/* SIMode */
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{
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unsigned int r;
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unsigned int a = 0x12488421u;
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unsigned int b = 0x88881111u;
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unsigned int csll = si_sll (b);
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unsigned int csrl = si_srl (b);
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r = rosbg_si_sll (a, b);
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if (r != (a | csll))
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__builtin_abort ();
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r = rosbg_si_srl (a, b);
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if (r != (a | csrl))
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__builtin_abort ();
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r = rxsbg_si_sll (a, b);
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if (r != (a ^ csll))
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__builtin_abort ();
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r = rxsbg_si_srl (a, b);
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if (r != (a ^ csrl))
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__builtin_abort ();
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}
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/* DIMode */
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{
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unsigned long long r;
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unsigned long long a = 0x1248357997538421lu;
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unsigned long long b = 0x8888444422221111lu;
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unsigned long long csll = di_sll (b);
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unsigned long long csrl = di_srl (b);
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r = rosbg_di_sll (a, b);
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if (r != (a | csll))
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__builtin_abort ();
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r = rosbg_di_srl (a, b);
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if (r != (a | csrl))
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__builtin_abort ();
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r = rxsbg_di_sll (a, b);
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if (r != (a ^ csll))
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__builtin_abort ();
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r = rxsbg_di_srl (a, b);
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if (r != (a ^ csrl))
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__builtin_abort ();
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}
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return 0;
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}
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@ -24,6 +24,17 @@ if ![istarget s390*-*-*] then {
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# Load support procs.
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load_lib gcc-dg.exp
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# Return 1 if z10 instructions work.
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proc check_effective_target_z10_instructions { } {
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if { ![check_runtime s390_check_z10_instructions [subst {
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int main (void)
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{
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asm ("rosbg %%r2,%%r2,0,0,0" : : );
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return 0;
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}
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}] "-march=z10 -mzarch" ] } { return 0 } else { return 1 }
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}
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# Return 1 if the the assembler understands .machine and .machinemode. The
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# target attribute needs that feature to work.
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proc check_effective_target_target_attribute { } {
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