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sh.h (TARGET_SH4A_ARCH): Remove macro.

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gcc/
	* config/sh/sh.h (TARGET_SH4A_ARCH): Remove macro.
	* config/sh/sh.h: Replace uses of TARGET_SH4A_ARCH with TARGET_SH4A.
	* config/sh/sh.c: Likewise.
	* config/sh/sh-mem.cc: Likewise.
	* config/sh/sh.md: Likewise.
	* config/sh/predicates.md: Likewise.
	* config/sh/sync.md: Likewise.

From-SVN: r216119
This commit is contained in:
Oleg Endo 2014-10-11 13:11:58 +00:00
parent 1665db4dbd
commit f3ca7111fb
7 changed files with 36 additions and 30 deletions
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10
gcc/ChangeLog
View file

@ -1,3 +1,13 @@
2014-10-11 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.h (TARGET_SH4A_ARCH): Remove macro.
* config/sh/sh.h: Replace uses of TARGET_SH4A_ARCH with TARGET_SH4A.
* config/sh/sh.c: Likewise.
* config/sh/sh-mem.cc: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sync.md: Likewise.
2014-10-11 Martin Liska <mliska@suse.cz>
PR/63376

4
gcc/config/sh/predicates.md
View file

@ -1074,14 +1074,14 @@
(and (match_test "satisfies_constraint_I08 (op)")
(match_test "mode != QImode")
(match_test "mode != HImode")
(match_test "TARGET_SH4A_ARCH"))))
(match_test "TARGET_SH4A"))))
(define_predicate "atomic_logical_operand"
(ior (match_code "subreg,reg")
(and (match_test "satisfies_constraint_K08 (op)")
(match_test "mode != QImode")
(match_test "mode != HImode")
(match_test "TARGET_SH4A_ARCH"))))
(match_test "TARGET_SH4A"))))
;; A predicate describing the T bit register in any form.
(define_predicate "t_reg_operand"

2
gcc/config/sh/sh-mem.cc
View file

@ -56,7 +56,7 @@ expand_block_move (rtx *operands)
/* If we could use mov.l to move words and dest is word-aligned, we
can use movua.l for loads and still generate a relatively short
and efficient sequence. */
if (TARGET_SH4A_ARCH && align < 4
if (TARGET_SH4A && align < 4
&& MEM_ALIGN (operands[0]) >= 32
&& can_move_by_pieces (bytes, 32))
{

4
gcc/config/sh/sh.c
View file

@ -818,7 +818,7 @@ sh_option_override (void)
assembler_dialect = 1;
sh_cpu = PROCESSOR_SH4;
}
if (TARGET_SH4A_ARCH)
if (TARGET_SH4A)
{
assembler_dialect = 1;
sh_cpu = PROCESSOR_SH4A;
@ -11597,7 +11597,7 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
if (TARGET_HARD_SH4 || TARGET_SH5)
{
if (!TARGET_INLINE_IC_INVALIDATE
|| (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
|| (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE))
emit_library_call (function_symbol (NULL, "__ic_invalidate",
FUNCTION_ORDINARY),
LCT_NORMAL, VOIDmode, 1, tramp, SImode);

6
gcc/config/sh/sh.h
View file

@ -70,13 +70,9 @@ extern int code_for_indirect_jump_scratch;
#undef TARGET_SH4
#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
/* Nonzero if we're generating code for the common subset of
instructions present on both SH4a and SH4al-dsp. */
#define TARGET_SH4A_ARCH TARGET_SH4A
/* Nonzero if we're generating code for SH4a, unless the use of the
FPU is disabled (which makes it compatible with SH4al-dsp). */
#define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
#define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
/* Nonzero if we should generate code using the SHcompact instruction
set and 32-bit ABI. */

16
gcc/config/sh/sh.md
View file

@ -6938,7 +6938,7 @@ label:
emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
DONE;
}
else if (TARGET_SH4A_ARCH || TARGET_SH4_300)
else if (TARGET_SH4A || TARGET_SH4_300)
{
emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
DONE;
@ -6971,7 +6971,7 @@ label:
(define_insn "ic_invalidate_line_sh4a"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
UNSPEC_ICACHE)]
"TARGET_SH4A_ARCH || TARGET_SH4_300"
"TARGET_SH4A || TARGET_SH4_300"
{
return "ocbwb @%0" "\n"
" synco" "\n"
@ -13487,7 +13487,7 @@ label:
[(set (match_operand:SI 0 "register_operand" "=z")
(unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
UNSPEC_MOVUA))]
"TARGET_SH4A_ARCH"
"TARGET_SH4A"
"movua.l %1,%0"
[(set_attr "type" "movua")])
@ -13500,7 +13500,7 @@ label:
(sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
(const_int 32) (const_int 0)))
(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
"TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
"TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
[(set (match_operand:SI 0 "register_operand" "")
(sign_extract:SI (mem:SI (post_inc:SI
(match_operand:SI 1 "register_operand" "")))
@ -13512,7 +13512,7 @@ label:
(sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
(match_operand 2 "const_int_operand" "")
(match_operand 3 "const_int_operand" "")))]
"TARGET_SH4A_ARCH || TARGET_SH2A"
"TARGET_SH4A || TARGET_SH2A"
{
if (TARGET_SH2A && TARGET_BITOPS
&& (satisfies_constraint_Sbw (operands[1])
@ -13525,7 +13525,7 @@ label:
emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
DONE;
}
if (TARGET_SH4A_ARCH
if (TARGET_SH4A
&& INTVAL (operands[2]) == 32
&& INTVAL (operands[3]) == 0
&& MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
@ -13544,7 +13544,7 @@ label:
(zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
(match_operand 2 "const_int_operand" "")
(match_operand 3 "const_int_operand" "")))]
"TARGET_SH4A_ARCH || TARGET_SH2A"
"TARGET_SH4A || TARGET_SH2A"
{
if (TARGET_SH2A && TARGET_BITOPS
&& (satisfies_constraint_Sbw (operands[1])
@ -13557,7 +13557,7 @@ label:
emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
DONE;
}
if (TARGET_SH4A_ARCH
if (TARGET_SH4A
&& INTVAL (operands[2]) == 32
&& INTVAL (operands[3]) == 0
&& MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)

24
gcc/config/sh/sync.md
View file

@ -224,7 +224,7 @@
rtx atomic_insn;
if (TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, addr,
exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
@ -264,7 +264,7 @@
(unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
|| (TARGET_SH4A && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
return "\r0: movli.l @%1,r0" "\n"
" cmp/eq %2,r0" "\n"
@ -437,7 +437,7 @@
rtx atomic_insn;
if (TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_exchange<mode>_hard (operands[0], addr, val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_exchange<mode>_soft_gusa (operands[0], addr, val);
@ -469,7 +469,7 @@
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
|| (TARGET_SH4A && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
return "\r0: movli.l @%1,r0" "\n"
" mov r0,%0" "\n"
@ -585,7 +585,7 @@
rtx atomic_insn;
if (TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_fetch_<fetchop_name><mode>_hard (operands[0], addr,
operands[2]);
else if (TARGET_ATOMIC_SOFT_GUSA)
@ -622,7 +622,7 @@
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
|| (TARGET_SH4A && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
return "\r0: movli.l @%1,r0" "\n"
" mov r0,%0" "\n"
@ -754,7 +754,7 @@
rtx atomic_insn;
if (TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_fetch_nand<mode>_hard (operands[0], addr,
operands[2]);
else if (TARGET_ATOMIC_SOFT_GUSA)
@ -791,7 +791,7 @@
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
|| (TARGET_SH4A && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
return "\r0: movli.l @%1,r0" "\n"
" mov r0,%0" "\n"
@ -932,7 +932,7 @@
rtx atomic_insn;
if (TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_<fetchop_name>_fetch<mode>_hard (operands[0], addr,
operands[2]);
else if (TARGET_ATOMIC_SOFT_GUSA)
@ -969,7 +969,7 @@
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
|| (TARGET_SH4A && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
return "\r0: movli.l @%1,%0" "\n"
" <fetchop_name> %2,%0" "\n"
@ -1099,7 +1099,7 @@
rtx atomic_insn;
if (TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_nand_fetch<mode>_hard (operands[0], addr,
operands[2]);
else if (TARGET_ATOMIC_SOFT_GUSA)
@ -1135,7 +1135,7 @@
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
|| (TARGET_SH4A && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
return "\r0: movli.l @%1,%0" "\n"
" and %2,%0" "\n"