RISC-V: Fix constraint bug for binary operation
Current constraint configuration will generate: vadd.vv v0,v24,v25,v0.t vsll.vx v0,v24,a5,v0.t They are incorrect according to RVV ISA. This patch fix this obvious issue. gcc/ChangeLog: * config/riscv/vector-iterators.md (sll.vi): Fix constraint bug. (sll.vv): Ditto. (%3,%4): Ditto. (%3,%v4): Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c:
This commit is contained in:
Ju-Zhe Zhong
Kito Cheng
parent
d8bd2c5f22
commit
f3a10f4fff
4 changed files with 75 additions and 69 deletions
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@ -229,42 +229,42 @@
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(umod "register_operand")])
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(define_code_attr binop_rhs1_constraint [
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(plus "vr,vr,vr")
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(minus "vr,vr,vi")
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(ior "vr,vr,vr")
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(xor "vr,vr,vr")
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(and "vr,vr,vr")
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(ashift "vr,vr,vr")
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(ashiftrt "vr,vr,vr")
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(lshiftrt "vr,vr,vr")
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(smin "vr,vr,vr")
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(smax "vr,vr,vr")
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(umin "vr,vr,vr")
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(umax "vr,vr,vr")
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(mult "vr,vr,vr")
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(div "vr,vr,vr")
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(mod "vr,vr,vr")
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(udiv "vr,vr,vr")
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(umod "vr,vr,vr")])
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(plus "vr,vr,vr,vr,vr,vr")
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(minus "vr,vr,vr,vr,vi,vi")
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(ior "vr,vr,vr,vr,vr,vr")
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(xor "vr,vr,vr,vr,vr,vr")
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(and "vr,vr,vr,vr,vr,vr")
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(ashift "vr,vr,vr,vr,vr,vr")
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(ashiftrt "vr,vr,vr,vr,vr,vr")
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(lshiftrt "vr,vr,vr,vr,vr,vr")
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(smin "vr,vr,vr,vr,vr,vr")
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(smax "vr,vr,vr,vr,vr,vr")
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(umin "vr,vr,vr,vr,vr,vr")
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(umax "vr,vr,vr,vr,vr,vr")
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(mult "vr,vr,vr,vr,vr,vr")
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(div "vr,vr,vr,vr,vr,vr")
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(mod "vr,vr,vr,vr,vr,vr")
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(udiv "vr,vr,vr,vr,vr,vr")
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(umod "vr,vr,vr,vr,vr,vr")])
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(define_code_attr binop_rhs2_constraint [
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(plus "vr,vi,vr")
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(minus "vr,vj,vr")
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(ior "vr,vi,vr")
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(xor "vr,vi,vr")
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(and "vr,vi,vr")
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(ashift "vr,vk,vr")
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(ashiftrt "vr,vk,vr")
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(lshiftrt "vr,vk,vr")
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(smin "vr,vr,vr")
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(smax "vr,vr,vr")
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(umin "vr,vr,vr")
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(umax "vr,vr,vr")
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(mult "vr,vr,vr")
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(div "vr,vr,vr")
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(mod "vr,vr,vr")
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(udiv "vr,vr,vr")
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(umod "vr,vr,vr")])
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(plus "vr,vr,vi,vi,vr,vr")
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(minus "vr,vr,vj,vj,vr,vr")
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(ior "vr,vr,vi,vi,vr,vr")
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(xor "vr,vr,vi,vi,vr,vr")
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(and "vr,vr,vi,vi,vr,vr")
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(ashift "vr,vr,vk,vk,vr,vr")
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(ashiftrt "vr,vr,vk,vk,vr,vr")
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(lshiftrt "vr,vr,vk,vk,vr,vr")
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(smin "vr,vr,vr,vr,vr,vr")
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(smax "vr,vr,vr,vr,vr,vr")
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(umin "vr,vr,vr,vr,vr,vr")
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(umax "vr,vr,vr,vr,vr,vr")
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(mult "vr,vr,vr,vr,vr,vr")
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(div "vr,vr,vr,vr,vr,vr")
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(mod "vr,vr,vr,vr,vr,vr")
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(udiv "vr,vr,vr,vr,vr,vr")
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(umod "vr,vr,vr,vr,vr,vr")])
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(define_code_attr int_binop_insn_type [
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(plus "vialu")
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@ -285,9 +285,9 @@
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(udiv "vidiv")
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(umod "vidiv")])
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;; <binop_alt1_insn> expands to the insn name of binop matching constraint alternative = 1.
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;; <binop_imm_rhs1_insn> expands to the insn name of binop matching constraint rhs1 is immediate.
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;; minus is negated as vadd and ss_minus is negated as vsadd, others remain <insn>.
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(define_code_attr binop_alt1_insn [(ashift "sll.vi")
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(define_code_attr binop_imm_rhs1_insn [(ashift "sll.vi")
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(ashiftrt "sra.vi")
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(lshiftrt "srl.vi")
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(div "div.vv")
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@ -305,9 +305,9 @@
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(umax "maxu.vv")
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(mult "mul.vv")])
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;; <binop_alt2_insn> expands to the insn name of binop matching constraint alternative = 2.
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;; <binop_imm_rhs2_insn> expands to the insn name of binop matching constraint rhs2 is immediate.
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;; minus is reversed as vrsub, others remain <insn>.
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(define_code_attr binop_alt2_insn [(ashift "sll.vv")
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(define_code_attr binop_imm_rhs2_insn [(ashift "sll.vv")
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(ashiftrt "sra.vv")
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(lshiftrt "srl.vv")
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(div "div.vv")
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@ -325,9 +325,9 @@
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(umax "maxu.vv")
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(mult "mul.vv")])
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(define_code_attr binop_alt1_op [(ashift "%3,%4")
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(ashiftrt "%3,%4")
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(lshiftrt "%3,%4")
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(define_code_attr binop_imm_rhs1_op [(ashift "%3,%v4")
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(ashiftrt "%3,%v4")
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(lshiftrt "%3,%v4")
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(div "%3,%4")
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(mod "%3,%4")
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(udiv "%3,%4")
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@ -335,7 +335,7 @@
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(ior "%3,%4")
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(xor "%3,%4")
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(and "%3,%4")
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(plus "%3,%4")
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(plus "%3,%v4")
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(minus "%3,%V4")
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(smin "%3,%4")
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(smax "%3,%4")
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@ -343,7 +343,7 @@
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(umax "%3,%4")
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(mult "%3,%4")])
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(define_code_attr binop_alt2_op [(ashift "%3,%4")
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(define_code_attr binop_imm_rhs2_op [(ashift "%3,%4")
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(ashiftrt "%3,%4")
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(lshiftrt "%3,%4")
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(div "%3,%4")
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@ -1127,25 +1127,28 @@
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;; -------------------------------------------------------------------------------
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(define_insn "@pred_<optab><mode>"
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[(set (match_operand:VI 0 "register_operand" "=vr, vr, vr")
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[(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr, vd, vr")
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(if_then_else:VI
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" " vmWc1,vmWc1,vmWc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(any_int_binop:VI
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(match_operand:VI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
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(match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
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(match_operand:VI 2 "vector_merge_operand" " 0vu, 0vu, 0vu")))]
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(match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu,0vu,0vu")))]
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"TARGET_VECTOR"
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"@
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v<insn>.vv\t%0,%3,%4%p1
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v<binop_alt1_insn>\t%0,<binop_alt1_op>%p1
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v<binop_alt2_insn>\t%0,<binop_alt2_op>%p1"
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v<insn>.vv\t%0,%3,%4%p1
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v<binop_imm_rhs1_insn>\t%0,<binop_imm_rhs1_op>%p1
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v<binop_imm_rhs1_insn>\t%0,<binop_imm_rhs1_op>%p1
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v<binop_imm_rhs2_insn>\t%0,<binop_imm_rhs2_op>%p1
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v<binop_imm_rhs2_insn>\t%0,<binop_imm_rhs2_op>%p1"
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[(set_attr "type" "<int_binop_insn_type>")
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(set_attr "mode" "<MODE>")])
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@ -1154,23 +1157,25 @@
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;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
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;; scalar mode is inner mode of the RVV mode for other vx patterns.
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(define_insn "@pred_<optab><mode>_scalar"
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[(set (match_operand:VI 0 "register_operand" "=vr, vr")
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[(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
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(if_then_else:VI
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1")
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(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(any_shift:VI
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(match_operand:VI 3 "register_operand" " vr, vr")
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(match_operand 4 "pmode_reg_or_uimm5_operand" " r, K"))
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(match_operand:VI 2 "vector_merge_operand" "0vu, 0vu")))]
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(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
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(match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, K, K"))
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(match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))]
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"TARGET_VECTOR"
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"@
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v<insn>.vx\t%0,%3,%4%p1
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v<insn>.vx\t%0,%3,%4%p1
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v<insn>.vi\t%0,%3,%4%p1
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v<insn>.vi\t%0,%3,%4%p1"
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[(set_attr "type" "vshift")
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(set_attr "mode" "<MODE>")])
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@ -29,7 +29,7 @@ void f1 (void * in, void *out)
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** vsetivli\tzero,4,e32,m1,ta,ma
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** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -52,7 +52,7 @@ void f2 (void * in, void *out)
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** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
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** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -93,7 +93,7 @@ void f4 (void * in, void *out)
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** vsetivli\tzero,4,e8,mf8,ta,ma
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** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -116,7 +116,7 @@ void f5 (void * in, void *out)
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** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
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** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
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** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
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** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -28,9 +28,10 @@ void f1 (void * in, void *out)
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** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
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** ...
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** vsetivli\tzero,4,e32,m1,ta,ma
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** ...
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** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
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** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
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** vsll\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
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** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -53,7 +54,7 @@ void f2 (void * in, void *out)
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** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
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** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17
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** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17,\s*v0.t
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** vsll\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*17,\s*v0.t
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** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -94,7 +95,7 @@ void f4 (void * in, void *out, size_t x)
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** vsetivli\tzero,4,e8,mf8,ta,ma
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** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5
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** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5,\s*v0.t
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** vsll\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*5,\s*v0.t
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** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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@ -117,7 +118,7 @@ void f5 (void * in, void *out)
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** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
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** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
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** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
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** vsll\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
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** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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