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re PR target/78604 (test case gcc.target/powerpc/p8vector-vectorize-1.c fails starting with r242750)

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PR target/78604
	* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Invert
	condition/operands for integer GE/LE/GEU/LEU operations.

	* gcc.target/powerpc/pr78604.c: New.

From-SVN: r245285
This commit is contained in:
Pat Haugen 2017-02-08 20:49:14 +00:00 • committed by Pat Haugen
parent fc00b9ced7
commit f39bad9fd0
4 changed files with 141 additions and 1 deletions
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6
gcc/ChangeLog
View file

@ -1,3 +1,9 @@
2017-02-08 Pat Haugen <pthaugen@us.ibm.com>
PR target/78604
* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Invert
condition/operands for integer GE/LE/GEU/LEU operations.
2017-02-08 Segher Boessenkool <segher@kernel.crashing.org>
PR translation/79397

19
gcc/config/rs6000/rs6000.c
View file

@ -25150,12 +25150,29 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
return 0;
break;
/* Mark unsigned tests with CCUNSmode. */
case GE:
case LE:
if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
{
/* Invert condition to avoid compound test. */
invert_move = true;
rcode = reverse_condition (rcode);
}
break;
case GTU:
case GEU:
case LTU:
case LEU:
/* Mark unsigned tests with CCUNSmode. */
cc_mode = CCUNSmode;
/* Invert condition to avoid compound test if necessary. */
if (rcode == GEU || rcode == LEU)
{
invert_move = true;
rcode = reverse_condition (rcode);
}
break;
default:

5
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2017-02-08 Pat Haugen <pthaugen@us.ibm.com>
PR target/78604
* gcc.target/powerpc/pr78604.c: New.
2017-02-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/68972

112
gcc/testsuite/gcc.target/powerpc/pr78604.c Normal file
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@ -0,0 +1,112 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize" } */
#ifndef SIZE
#define SIZE 1024
#endif
#ifndef ALIGN
#define ALIGN 32
#endif
#ifndef TYPE
#define TYPE long long
#endif
#ifndef SIGN_TYPE
#define SIGN_TYPE signed TYPE
#endif
#ifndef UNS_TYPE
#define UNS_TYPE unsigned TYPE
#endif
#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
SIGN_TYPE sa[SIZE] ALIGN_ATTR;
SIGN_TYPE sb[SIZE] ALIGN_ATTR;
SIGN_TYPE sc[SIZE] ALIGN_ATTR;
UNS_TYPE ua[SIZE] ALIGN_ATTR;
UNS_TYPE ub[SIZE] ALIGN_ATTR;
UNS_TYPE uc[SIZE] ALIGN_ATTR;
void
sign_lt (SIGN_TYPE val1, SIGN_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
sa[i] = (sb[i] < sc[i]) ? val1 : val2;
}
void
sign_lte (SIGN_TYPE val1, SIGN_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
sa[i] = (sb[i] <= sc[i]) ? val1 : val2;
}
void
sign_gt (SIGN_TYPE val1, SIGN_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
sa[i] = (sb[i] > sc[i]) ? val1 : val2;
}
void
sign_gte (SIGN_TYPE val1, SIGN_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
sa[i] = (sb[i] >= sc[i]) ? val1 : val2;
}
void
uns_lt (UNS_TYPE val1, UNS_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
ua[i] = (ub[i] < uc[i]) ? val1 : val2;
}
void
uns_lte (UNS_TYPE val1, UNS_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
ua[i] = (ub[i] <= uc[i]) ? val1 : val2;
}
void
uns_gt (UNS_TYPE val1, UNS_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
ua[i] = (ub[i] > uc[i]) ? val1 : val2;
}
void
uns_gte (UNS_TYPE val1, UNS_TYPE val2)
{
unsigned long i;
for (i = 0; i < SIZE; i++)
ua[i] = (ub[i] >= uc[i]) ? val1 : val2;
}
/* { dg-final { scan-assembler-times {\mvcmpgtsd\M} 4 } } */
/* { dg-final { scan-assembler-times {\mvcmpgtud\M} 4 } } */
/* { dg-final { scan-assembler-not {\mvcmpequd\M} } } */