From f348741d28f3036bbef62bf072fe212fa02b15e2 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 23 Jul 2007 12:04:48 +0000 Subject: [PATCH] constraints.md (ks): New constraint. gcc/ * config/mips/constraints.md (ks): New constraint. * config/mips/mips.md (*add3_sp1, *add3_sp2): Fold into... (*add3_mips16): ...here and fix their length calculations. From-SVN: r126842 --- gcc/ChangeLog | 6 +++++ gcc/config/mips/constraints.md | 7 ++++++ gcc/config/mips/mips.md | 45 +++++++++------------------------- 3 files changed, 25 insertions(+), 33 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5d4982d47b7..afb13127b3b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2007-07-23 Richard Sandiford + + * config/mips/constraints.md (ks): New constraint. + * config/mips/mips.md (*add3_sp1, *add3_sp2): Fold into... + (*add3_mips16): ...here and fix their length calculations. + 2007-07-21 Uros Bizjak * optabs.h (enum optab_index): Add new OTI_signbit. diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 5b184e2b69a..8a63c2e670c 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -83,6 +83,13 @@ ;; but the DSPr2 version allows any accumulator target. (define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS") +;; This is a normal rather than a register constraint because we can +;; never use the stack pointer as a reload register. +(define_constraint "ks" + "@internal" + (and (match_code "reg") + (match_test "REGNO (op) == STACK_POINTER_REGNUM"))) + ;; Integer constraints (define_constraint "I" diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 0a060aa19cf..58bf81d2ddb 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -739,47 +739,27 @@ [(set_attr "type" "arith") (set_attr "mode" "")]) -;; We need to recognize MIPS16 stack pointer additions explicitly, since -;; we don't have a constraint for $sp. These insns will be generated by -;; the save_restore_insns functions. - -(define_insn "*add3_sp1" - [(set (reg:GPR 29) - (plus:GPR (reg:GPR 29) - (match_operand:GPR 0 "const_arith_operand" "")))] - "TARGET_MIPS16" - "addiu\t%$,%$,%0" - [(set_attr "type" "arith") - (set_attr "mode" "") - (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8") - (const_int 4) - (const_int 8)))]) - -(define_insn "*add3_sp2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (plus:GPR (reg:GPR 29) - (match_operand:GPR 1 "const_arith_operand" "")))] - "TARGET_MIPS16" - "addiu\t%0,%$,%1" - [(set_attr "type" "arith") - (set_attr "mode" "") - (set (attr "length") (if_then_else (match_operand 1 "m16_uimm_4") - (const_int 4) - (const_int 8)))]) - (define_insn "*add3_mips16" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d") - (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d") - (match_operand:GPR 2 "arith_operand" "Q,O,d")))] + [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d") + (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d") + (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))] "TARGET_MIPS16" "@ + addiu\t%0,%2 + addiu\t%0,%1,%2 addiu\t%0,%2 addiu\t%0,%1,%2 addu\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "") (set_attr_alternative "length" - [(if_then_else (match_operand 2 "m16_simm_1") + [(if_then_else (match_operand 2 "m16_simm8_8") + (const_int 4) + (const_int 8)) + (if_then_else (match_operand 2 "m16_uimm_4") + (const_int 4) + (const_int 8)) + (if_then_else (match_operand 2 "m16_simm_1") (const_int 4) (const_int 8)) (if_then_else (match_operand 2 "m16_simm4_1") @@ -787,7 +767,6 @@ (const_int 8)) (const_int 4)])]) - ;; On the mips16, we can sometimes split an add of a constant which is ;; a 4 byte instruction into two adds which are both 2 byte ;; instructions. There are two cases: one where we are adding a