Make Niagara-4 instruction scheduling more accurate.
* config/sparc/sparc.md (type attribute): Add new types 'visl' (VIS logical operation), 'vismv' (VIS move), and 'pdistn'. Rename 'fgm_pdist' to 'pdist'. (*movsi_insn): Use vismv and visl. (*movdi_insn_sp64): Likewise. (*movsf_insn): Likewise. (*movdf_insn_sp64): Likewise. (*mov<VM32:mode>_insn): Likewise, use 'fsrc2s' instead of 'fsrc1s'. (*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s' instead of 'fsrc1s'. (*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s' instead of 'fsrc1s'. (VIS logical instructions): Mark as visl. (pdist_vis): Use 'pdist'. (pditsn<mode>_vis): Use 'pdistn'. * config/sparc/ultra1_2.md: Adjust for new VIS attribute types. * config/sparc/ultra3.md: Likewise. * config/sparc/niagara.md: Likewise. * config/sparc/niagara2.md: Likewise. * config/sparc/niagara4.md: Add cpu units "n4_slot2" and "n4_load_store" for special store scheduling. Use them in load and store reservations. Integer divide and multiply can only issue in slot-1. Represent 1-cycle VIS moves and 3-cycle VIS logic operations. From-SVN: r192286
This commit is contained in:
David S. Miller
David S. Miller
parent
e368f44fef
commit
f298688cb7
7 changed files with 96 additions and 40 deletions
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@ -1,3 +1,28 @@
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2012-10-09 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc.md (type attribute): Add new types 'visl'
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(VIS logical operation), 'vismv' (VIS move), and 'pdistn'. Rename
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'fgm_pdist' to 'pdist'.
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(*movsi_insn): Use vismv and visl.
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(*movdi_insn_sp64): Likewise.
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(*movsf_insn): Likewise.
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(*movdf_insn_sp64): Likewise.
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(*mov<VM32:mode>_insn): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
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(*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
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(*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
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(VIS logical instructions): Mark as visl.
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(pdist_vis): Use 'pdist'.
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(pditsn<mode>_vis): Use 'pdistn'.
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* config/sparc/ultra1_2.md: Adjust for new VIS attribute types.
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* config/sparc/ultra3.md: Likewise.
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* config/sparc/niagara.md: Likewise.
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* config/sparc/niagara2.md: Likewise.
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* config/sparc/niagara4.md: Add cpu units "n4_slot2" and
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"n4_load_store" for special store scheduling. Use them in load
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and store reservations. Integer divide and multiply can only
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issue in slot-1. Represent 1-cycle VIS moves and 3-cycle VIS
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logic operations.
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2012-10-10 Dehao Chen <dehao@google.com>
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* tree-eh.c (lower_try_finally_onedest): Set correct location for
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@ -114,5 +114,5 @@
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*/
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(define_insn_reservation "niag_vis" 8
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,gsr,array"))
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(eq_attr "type" "fga,visl,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array"))
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"niag_pipe*8")
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@ -111,10 +111,10 @@
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(define_insn_reservation "niag2_vis" 6
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,array,gsr"))
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(eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,edge,edgen,array,gsr"))
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"niag2_pipe*6")
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(define_insn_reservation "niag3_vis" 9
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,array,gsr"))
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(eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,gsr"))
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"niag2_pipe*9")
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@ -19,12 +19,14 @@
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(define_automaton "niagara4_0")
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(define_cpu_unit "n4_slot0,n4_slot1" "niagara4_0")
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(define_reservation "n4_single_issue" "n4_slot0 + n4_slot1")
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(define_cpu_unit "n4_slot0,n4_slot1,n4_slot2" "niagara4_0")
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(define_reservation "n4_single_issue" "n4_slot0 + n4_slot1 + n4_slot2")
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(define_cpu_unit "n4_load_store" "niagara4_0")
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(define_insn_reservation "n4_single" 1
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "multi,savew,flushw,iflush,trap,gsr"))
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(eq_attr "type" "multi,savew,flushw,iflush,trap"))
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"n4_single_issue")
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(define_insn_reservation "n4_integer" 1
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@ -35,22 +37,22 @@
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(define_insn_reservation "n4_imul" 12
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "imul"))
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"(n4_slot0 | n4_slot1), nothing*11")
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"n4_slot1, nothing*11")
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(define_insn_reservation "n4_idiv" 35
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "idiv"))
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"(n4_slot0 | n4_slot1), nothing*34")
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"n4_slot1, nothing*34")
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(define_insn_reservation "n4_load" 5
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "load,fpload,sload"))
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"n4_slot0, nothing*4")
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"(n4_slot0 + n4_load_store), nothing*4")
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(define_insn_reservation "n4_store" 1
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "store,fpstore"))
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"n4_slot0")
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"(n4_slot0 | n4_slot2) + n4_load_store")
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(define_insn_reservation "n4_cti" 2
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(and (eq_attr "cpu" "niagara4")
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@ -67,9 +69,38 @@
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(eq_attr "type" "array,edge,edgen"))
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"n4_slot1, nothing*11")
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(define_insn_reservation "n4_vis" 11
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(define_insn_reservation "n4_vis_move_1cycle" 1
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist"))
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(and (eq_attr "type" "vismv")
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(eq_attr "fptype" "double")))
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"n4_slot1")
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(define_insn_reservation "n4_vis_move_11cycle" 11
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(and (eq_attr "cpu" "niagara4")
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(and (eq_attr "type" "vismv")
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(eq_attr "fptype" "single")))
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"n4_slot1, nothing*10")
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(define_insn_reservation "n4_vis_logical" 3
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(and (eq_attr "cpu" "niagara4")
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(and (eq_attr "type" "visl,pdistn")
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(eq_attr "fptype" "double")))
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"n4_slot1, nothing*2")
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(define_insn_reservation "n4_vis_logical_11cycle" 11
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(and (eq_attr "cpu" "niagara4")
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(and (eq_attr "type" "visl")
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(eq_attr "fptype" "single")))
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"n4_slot1, nothing*10")
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(define_insn_reservation "n4_vis_fga" 11
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "fga,gsr"))
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"n4_slot1, nothing*10")
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(define_insn_reservation "n4_vis_fgm" 11
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(and (eq_attr "cpu" "niagara4")
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(eq_attr "type" "fgm_pack,fgm_mul,pdist"))
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"n4_slot1, nothing*10")
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(define_insn_reservation "n4_fpdivs" 24
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@ -264,7 +264,7 @@
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fpcmp,
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fpmul,fpdivs,fpdivd,
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fpsqrts,fpsqrtd,
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fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,gsr,array,
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fga,visl,vismv,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,
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cmove,
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ialuX,
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multi,savew,flushw,iflush,trap"
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@ -1457,7 +1457,7 @@
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st\t%1, %0
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fzeros\t%0
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fones\t%0"
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[(set_attr "type" "*,*,load,store,*,*,fpmove,fpload,fpstore,fga,fga")
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[(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
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(set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")])
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(define_insn "*movsi_lo_sum"
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@ -1622,7 +1622,7 @@
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std\t%1, %0
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fzero\t%0
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fone\t%0"
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[(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,*,*,*,fpload,fpstore,fga,fga")
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[(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl")
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(set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,2,2,2,*,*,*,*")
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(set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double")
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(set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")])
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@ -1645,7 +1645,7 @@
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std\t%1, %0
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fzero\t%0
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fone\t%0"
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[(set_attr "type" "*,*,load,store,*,*,fpmove,fpload,fpstore,fga,fga")
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[(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
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(set_attr "fptype" "*,*,*,*,*,*,double,*,*,double,double")
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(set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")])
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@ -2251,7 +2251,7 @@
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "fga,fga,fpmove,*,*,*,*,*,fpload,load,fpstore,store")
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[(set_attr "type" "visl,visl,fpmove,*,*,*,vismv,vismv,fpload,load,fpstore,store")
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(set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")])
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;; The following 3 patterns build SFmode constants in integer registers.
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@ -2323,7 +2323,7 @@
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#
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#
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#"
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[(set_attr "type" "fga,fga,fpmove,*,*,*,fpload,store,fpstore,load,store,*,*,*,*")
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[(set_attr "type" "visl,visl,fpmove,*,*,*,fpload,store,fpstore,load,store,*,*,*,*")
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(set_attr "length" "*,*,*,2,2,2,*,*,*,*,*,2,2,2,2")
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(set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*,*,*,*,*")
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(set_attr "cpu_feature" "vis,vis,v9,fpunotv9,vis3,vis3,fpu,v9,fpu,*,*,fpu,*,*,fpu")])
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@ -2346,7 +2346,7 @@
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ldx\t%1, %0
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stx\t%r1, %0
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#"
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[(set_attr "type" "fga,fga,fpmove,*,*,load,store,*,load,store,*")
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[(set_attr "type" "visl,visl,fpmove,vismv,vismv,load,store,*,load,store,*")
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(set_attr "length" "*,*,*,*,*,*,*,*,*,*,2")
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(set_attr "fptype" "double,double,double,double,double,*,*,*,*,*,*")
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(set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")])
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@ -7876,7 +7876,7 @@
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"@
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fzeros\t%0
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fones\t%0
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fsrc1s\t%1, %0
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fsrc2s\t%1, %0
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ld\t%1, %0
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st\t%1, %0
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st\t%r1, %0
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@ -7885,7 +7885,7 @@
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mov\t%1, %0
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movstouw\t%1, %0
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movwtos\t%1, %0"
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[(set_attr "type" "fga,fga,fga,fpload,fpstore,store,load,store,*,*,*")
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[(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,*,vismv,vismv")
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(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")])
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(define_insn "*mov<VM64:mode>_insn_sp64"
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@ -7898,7 +7898,7 @@
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"@
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fzero\t%0
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fone\t%0
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fsrc1\t%1, %0
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fsrc2\t%1, %0
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ldd\t%1, %0
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std\t%1, %0
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stx\t%r1, %0
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@ -7907,7 +7907,7 @@
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movdtox\t%1, %0
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movxtod\t%1, %0
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mov\t%1, %0"
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[(set_attr "type" "fga,fga,fga,fpload,fpstore,store,load,store,*,*,*")
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[(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,vismv,vismv,*")
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(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")])
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(define_insn "*mov<VM64:mode>_insn_sp32"
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@ -7920,7 +7920,7 @@
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"@
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fzero\t%0
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fone\t%0
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fsrc1\t%1, %0
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fsrc2\t%1, %0
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#
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#
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ldd\t%1, %0
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@ -7930,7 +7930,7 @@
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std\t%1, %0
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#
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#"
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[(set_attr "type" "fga,fga,fga,*,*,fpload,fpstore,store,load,store,*,*")
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[(set_attr "type" "visl,visl,vismv,*,*,fpload,fpstore,store,load,store,*,*")
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(set_attr "length" "*,*,*,2,2,*,*,*,*,*,2,2")
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(set_attr "cpu_feature" "vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*")])
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@ -8025,7 +8025,7 @@
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(match_operand:VL 2 "register_operand" "<vconstr>")))]
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"TARGET_VIS"
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"f<vlinsn><vlsuf>\t%1, %2, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "<vfptype>")])
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(define_insn "*not_<code><mode>3"
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@ -8034,7 +8034,7 @@
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(match_operand:VL 2 "register_operand" "<vconstr>"))))]
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"TARGET_VIS"
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"f<vlninsn><vlsuf>\t%1, %2, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "<vfptype>")])
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;; (ior (not (op1)) (not (op2))) is the canonical form of NAND.
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@ -8044,7 +8044,7 @@
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(not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))]
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"TARGET_VIS"
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"fnand<vlsuf>\t%1, %2, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "<vfptype>")])
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(define_code_iterator vlnotop [ior and])
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@ -8055,7 +8055,7 @@
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(match_operand:VL 2 "register_operand" "<vconstr>")))]
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"TARGET_VIS"
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"f<vlinsn>not1<vlsuf>\t%1, %2, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "<vfptype>")])
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(define_insn "*<code>_not2<mode>_vis"
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@ -8064,7 +8064,7 @@
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(not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))]
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"TARGET_VIS"
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"f<vlinsn>not2<vlsuf>\t%1, %2, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "<vfptype>")])
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(define_insn "one_cmpl<mode>2"
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@ -8072,7 +8072,7 @@
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(not:VL (match_operand:VL 1 "register_operand" "<vconstr>")))]
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"TARGET_VIS"
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"fnot1<vlsuf>\t%1, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "<vfptype>")])
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;; Hard to generate VIS instructions. We have builtins for these.
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@ -8351,7 +8351,7 @@
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UNSPEC_PDIST))]
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"TARGET_VIS"
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"pdist\t%1, %2, %0"
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[(set_attr "type" "fgm_pdist")
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[(set_attr "type" "pdist")
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(set_attr "fptype" "double")])
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;; Edge instructions produce condition codes equivalent to a 'subcc'
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@ -8433,7 +8433,7 @@
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UNSPEC_FCMP))]
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"TARGET_VIS"
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"fcmp<code><GCM:gcm_name>\t%1, %2, %0"
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[(set_attr "type" "fga")
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[(set_attr "type" "visl")
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(set_attr "fptype" "double")])
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(define_expand "vcond<mode><mode>"
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@ -8674,7 +8674,7 @@
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UNSPEC_PDISTN))]
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"TARGET_VIS3"
|
||||
"pdistn\t%1, %2, %0"
|
||||
[(set_attr "type" "fgm_pdist")
|
||||
[(set_attr "type" "pdistn")
|
||||
(set_attr "fptype" "double")])
|
||||
|
||||
(define_insn "fmean16_vis"
|
||||
|
|
@ -8724,7 +8724,7 @@
|
|||
UNSPEC_FUCMP))]
|
||||
"TARGET_VIS3"
|
||||
"fucmp<code>8\t%1, %2, %0"
|
||||
[(set_attr "type" "fga")])
|
||||
[(set_attr "type" "visl")])
|
||||
|
||||
(define_insn "*naddsf3"
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
|
|
|
|||
|
|
@ -255,7 +255,7 @@
|
|||
2
|
||||
(and (and
|
||||
(eq_attr "cpu" "ultrasparc")
|
||||
(eq_attr "type" "fga"))
|
||||
(eq_attr "type" "fga,visl,vismv"))
|
||||
(eq_attr "fptype" "single"))
|
||||
"us1_fpa + us1_fp_single + us1_slotany, nothing")
|
||||
|
||||
|
|
@ -265,7 +265,7 @@
|
|||
2
|
||||
(and (and
|
||||
(eq_attr "cpu" "ultrasparc")
|
||||
(eq_attr "type" "fga"))
|
||||
(eq_attr "type" "fga,visl,vismv"))
|
||||
(eq_attr "fptype" "double"))
|
||||
"us1_fpa + us1_fp_double + us1_slotany, nothing")
|
||||
|
||||
|
|
@ -294,7 +294,7 @@
|
|||
(define_insn_reservation "us1_pdist"
|
||||
4
|
||||
(and (eq_attr "cpu" "ultrasparc")
|
||||
(eq_attr "type" "fgm_pdist"))
|
||||
(eq_attr "type" "pdist"))
|
||||
"us1_fpm + us1_fp_double + us1_slotany, nothing*3")
|
||||
|
||||
(define_bypass 3 "us1_pdist" "us1_fga_double,us1_fga_single")
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@
|
|||
(define_insn_reservation "us3_fga"
|
||||
3
|
||||
(and (eq_attr "cpu" "ultrasparc3")
|
||||
(eq_attr "type" "fga"))
|
||||
(eq_attr "type" "fga,visl,vismv"))
|
||||
"us3_fpa + us3_slotany, nothing*2")
|
||||
|
||||
(define_insn_reservation "us3_fgm"
|
||||
|
|
@ -188,7 +188,7 @@
|
|||
(define_insn_reservation "us3_pdist"
|
||||
4
|
||||
(and (eq_attr "cpu" "ultrasparc3")
|
||||
(eq_attr "type" "fgm_pdist"))
|
||||
(eq_attr "type" "pdist"))
|
||||
"us3_fpm + us3_slotany, nothing*3")
|
||||
|
||||
(define_bypass 1 "us3_pdist" "us3_pdist")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue