From f192bf8b22b4512bac0479435a5c3d4a33ad13c3 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Thu, 16 Oct 1997 01:37:11 +0000 Subject: [PATCH] Add patch from Edelsohn From-SVN: r15918 --- gcc/ChangeLog | 7 ++ gcc/config/rs6000/rs6000.md | 128 ++++++++++++++++++++++++++++++------ 2 files changed, 116 insertions(+), 19 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 368d21281df..41fb7afa648 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +Wed Oct 15 21:34:45 1997 David Edelsohn + + * rs6000.md (udivsi3, divsi3): Split into MQ and non-MQ cases for + PPC601. + (umulsidi3,umulsi3_highpart): Ditto. + (smulsi3_highpart_no_mq): Add !TARGET_POWER. + Wed Oct 15 18:21:46 1997 Richard Henderson * alpha.c (final_prescan_insn): Gut, remove and transform to ... diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f529ad875e3..ce2435edc66 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1388,14 +1388,6 @@ "divs %0,%1,%2" [(set_attr "type" "idiv")]) -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")))] - "TARGET_POWERPC" - "divw %0,%1,%2" - [(set_attr "type" "idiv")]) - (define_expand "udivsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -1411,13 +1403,27 @@ emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); DONE; } + else if (TARGET_POWER) + { + emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); + DONE; + } }") -(define_insn "" +(define_insn "udivsi3_mq" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) + (clobber (match_scratch:SI 3 "=q"))] + "TARGET_POWERPC && TARGET_POWER" + "divwu %0,%1,%2" + [(set_attr "type" "idiv")]) + +(define_insn "*udivsi3_no_mq" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r")))] - "TARGET_POWERPC" + "TARGET_POWERPC && ! TARGET_POWER" "divwu %0,%1,%2" [(set_attr "type" "idiv")]) @@ -1436,7 +1442,14 @@ && exact_log2 (INTVAL (operands[2])) >= 0) ; else if (TARGET_POWERPC) - operands[2] = force_reg (SImode, operands[2]); + { + operands[2] = force_reg (SImode, operands[2]); + if (TARGET_POWER) + { + emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); + DONE; + } + } else if (TARGET_POWER) FAIL; else @@ -1449,6 +1462,23 @@ } }") +(define_insn "divsi3_mq" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) + (clobber (match_scratch:SI 3 "=q"))] + "TARGET_POWERPC && TARGET_POWER" + "divw %0,%1,%2" + [(set_attr "type" "idiv")]) + +(define_insn "*divsi3_no_mq" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "TARGET_POWERPC && ! TARGET_POWER" + "divw %0,%1,%2" + [(set_attr "type" "idiv")]) + (define_expand "modsi3" [(use (match_operand:SI 0 "gpc_reg_operand" "")) (use (match_operand:SI 1 "gpc_reg_operand" "")) @@ -4020,11 +4050,11 @@ [(set_attr "type" "imul") (set_attr "length" "8")]) -(define_insn "*mulsidi3_powerpc" +(define_insn "*mulsidi3_no_mq" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "TARGET_POWERPC && ! TARGET_POWERPC64" + "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" "* { return (WORDS_BIG_ENDIAN) @@ -4054,11 +4084,40 @@ operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); }") -(define_insn "umulsidi3" +(define_expand "umulsidi3" + [(set (match_operand:DI 0 "gpc_reg_operand" "") + (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) + (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] + "TARGET_POWERPC && ! TARGET_POWERPC64" + " +{ + if (TARGET_POWER) + { + emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "umulsidi3_mq" + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) + (clobber (match_scratch:SI 3 "=q"))] + "TARGET_POWERPC && TARGET_POWER" + "* +{ + return (WORDS_BIG_ENDIAN) + ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" + : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "length" "8")]) + +(define_insn "*umulsidi3_no_mq" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "TARGET_POWERPC && ! TARGET_POWERPC64" + "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" "* { return (WORDS_BIG_ENDIAN) @@ -4127,7 +4186,7 @@ "mul %0,%1,%2" [(set_attr "type" "imul")]) -(define_insn "" +(define_insn "*smulsi3_highpart_no_mq" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI @@ -4135,11 +4194,42 @@ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 32))))] - "TARGET_POWERPC" + "TARGET_POWERPC && ! TARGET_POWER" "mulhw %0,%1,%2" [(set_attr "type" "imul")]) -(define_insn "umulsi3_highpart" +(define_expand "umulsi3_highpart" + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI + (match_operand:SI 1 "gpc_reg_operand" "")) + (zero_extend:DI + (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 32))))] + "TARGET_POWERPC" + " +{ + if (TARGET_POWER) + { + emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "umulsi3_highpart_mq" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI + (match_operand:SI 1 "gpc_reg_operand" "%r")) + (zero_extend:DI + (match_operand:SI 2 "gpc_reg_operand" "r"))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "=q"))] + "TARGET_POWERPC && TARGET_POWER" + "mulhwu %0,%1,%2" + [(set_attr "type" "imul")]) + +(define_insn "*umulsi3_highpart_no_mq" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI @@ -4147,7 +4237,7 @@ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 32))))] - "TARGET_POWERPC" + "TARGET_POWERPC && ! TARGET_POWER" "mulhwu %0,%1,%2" [(set_attr "type" "imul")])