rs6000, Add test 128-bit shifts for just the int128 type.
This patch also renames and moves the VSX_TI iterator from vsx.md to VEC_TI in vector.md. The uses of VEC_TI are also updated. 2021-04-29 Carl Love <cel@us.ibm.com> gcc/ChangeLog * config/rs6000/altivec.md (altivec_vslq, altivec_vsrq): Rename to altivec_vslq_<mode>, altivec_vsrq_<mode>, mode VEC_TI. * config/rs6000/vector.md (VEC_TI): Was named VSX_TI in vsx.md. (vashlv1ti3): Change to vashl<mode>3, mode VEC_TI. (vlshrv1ti3): Change to vlshr<mode>3, mode VEC_TI. * config/rs6000/vsx.md (VSX_TI): Remove define_mode_iterator. Update uses of VSX_TI to VEC_TI. gcc/testsuite/ChangeLog * gcc.target/powerpc/int_128bit-runnable.c: Add shift_right, shift_left tests.
This commit is contained in:
Carl Love
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976ffcf87d
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4 changed files with 52 additions and 40 deletions
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@ -2226,10 +2226,10 @@
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"vsl<VI_char> %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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(define_insn "altivec_vslq"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
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(ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
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(match_operand:V1TI 2 "vsx_register_operand" "v")))]
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(define_insn "altivec_vslq_<mode>"
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[(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v")
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(ashift:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand" "v")
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(match_operand:VEC_TI 2 "vsx_register_operand" "v")))]
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"TARGET_POWER10"
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/* Shift amount in needs to be in bits[57:63] of 128-bit operand. */
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"vslq %0,%1,%2"
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@ -2243,10 +2243,10 @@
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"vsr<VI_char> %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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(define_insn "altivec_vsrq"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
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(lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
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(match_operand:V1TI 2 "vsx_register_operand" "v")))]
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(define_insn "altivec_vsrq_<mode>"
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[(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v")
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(lshiftrt:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand" "v")
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(match_operand:VEC_TI 2 "vsx_register_operand" "v")))]
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"TARGET_POWER10"
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/* Shift amount in needs to be in bits[57:63] of 128-bit operand. */
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"vsrq %0,%1,%2"
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@ -26,6 +26,9 @@
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;; Vector int modes
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(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])
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;; 128-bit int modes
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(define_mode_iterator VEC_TI [V1TI TI])
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;; Vector int modes for parity
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(define_mode_iterator VEC_IP [V8HI
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V4SI
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@ -1620,17 +1623,17 @@
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"")
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;; No immediate version of this 128-bit instruction
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(define_expand "vashlv1ti3"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
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(ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
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(match_operand:V1TI 2 "vsx_register_operand" "v")))]
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(define_expand "vashl<mode>3"
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[(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v")
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(ashift:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand")
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(match_operand:VEC_TI 2 "vsx_register_operand")))]
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"TARGET_POWER10"
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{
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/* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */
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rtx tmp = gen_reg_rtx (V1TImode);
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rtx tmp = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
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emit_insn (gen_altivec_vslq (operands[0], operands[1], tmp));
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emit_insn(gen_altivec_vslq_<mode> (operands[0], operands[1], tmp));
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DONE;
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})
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@ -1643,17 +1646,17 @@
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"")
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;; No immediate version of this 128-bit instruction
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(define_expand "vlshrv1ti3"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
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(lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
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(match_operand:V1TI 2 "vsx_register_operand" "v")))]
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(define_expand "vlshr<mode>3"
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[(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v")
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(lshiftrt:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand")
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(match_operand:VEC_TI 2 "vsx_register_operand")))]
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"TARGET_POWER10"
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{
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/* Shift amount in needs to be put into bits[57:63] of 128-bit operand2. */
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rtx tmp = gen_reg_rtx (V1TImode);
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rtx tmp = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
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emit_insn (gen_altivec_vsrq (operands[0], operands[1], tmp));
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emit_insn(gen_altivec_vsrq_<mode> (operands[0], operands[1], tmp));
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DONE;
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})
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@ -37,9 +37,6 @@
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TI
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V1TI])
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;; Iterator for 128-bit integer types that go in a single vector register.
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(define_mode_iterator VSX_TI [TI V1TI])
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;; Iterator for the 2 32-bit vector types
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(define_mode_iterator VSX_W [V4SF V4SI])
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@ -952,9 +949,9 @@
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;; special V1TI container class, which it is not appropriate to use vec_select
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;; for the type.
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(define_insn "*vsx_le_permute_<mode>"
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[(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=wa,wa,Z,&r,&r,Q")
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(rotate:VSX_TI
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(match_operand:VSX_TI 1 "input_operand" "wa,Z,wa,r,Q,r")
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[(set (match_operand:VEC_TI 0 "nonimmediate_operand" "=wa,wa,Z,&r,&r,Q")
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(rotate:VEC_TI
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(match_operand:VEC_TI 1 "input_operand" "wa,Z,wa,r,Q,r")
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(const_int 64)))]
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"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
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"@
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@ -968,10 +965,10 @@
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(set_attr "type" "vecperm,vecload,vecstore,*,load,store")])
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(define_insn_and_split "*vsx_le_undo_permute_<mode>"
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[(set (match_operand:VSX_TI 0 "vsx_register_operand" "=wa,wa")
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(rotate:VSX_TI
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(rotate:VSX_TI
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(match_operand:VSX_TI 1 "vsx_register_operand" "0,wa")
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[(set (match_operand:VEC_TI 0 "vsx_register_operand" "=wa,wa")
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(rotate:VEC_TI
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(rotate:VEC_TI
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(match_operand:VEC_TI 1 "vsx_register_operand" "0,wa")
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(const_int 64))
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(const_int 64)))]
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"!BYTES_BIG_ENDIAN && TARGET_VSX"
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@ -1043,11 +1040,11 @@
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;; Peepholes to catch loads and stores for TImode if TImode landed in
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;; GPR registers on a little endian system.
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(define_peephole2
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[(set (match_operand:VSX_TI 0 "int_reg_operand")
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(rotate:VSX_TI (match_operand:VSX_TI 1 "memory_operand")
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[(set (match_operand:VEC_TI 0 "int_reg_operand")
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(rotate:VEC_TI (match_operand:VEC_TI 1 "memory_operand")
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(const_int 64)))
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(set (match_operand:VSX_TI 2 "int_reg_operand")
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(rotate:VSX_TI (match_dup 0)
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(set (match_operand:VEC_TI 2 "int_reg_operand")
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(rotate:VEC_TI (match_dup 0)
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(const_int 64)))]
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"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
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&& (rtx_equal_p (operands[0], operands[2])
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@ -1055,11 +1052,11 @@
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[(set (match_dup 2) (match_dup 1))])
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(define_peephole2
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[(set (match_operand:VSX_TI 0 "int_reg_operand")
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(rotate:VSX_TI (match_operand:VSX_TI 1 "int_reg_operand")
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[(set (match_operand:VEC_TI 0 "int_reg_operand")
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(rotate:VEC_TI (match_operand:VEC_TI 1 "int_reg_operand")
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(const_int 64)))
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(set (match_operand:VSX_TI 2 "memory_operand")
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(rotate:VSX_TI (match_dup 0)
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(set (match_operand:VEC_TI 2 "memory_operand")
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(rotate:VEC_TI (match_dup 0)
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(const_int 64)))]
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"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
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&& peep2_reg_dead_p (2, operands[0])"
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@ -52,6 +52,18 @@ void print_i128(__int128_t val)
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void abort (void);
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__attribute__((noinline))
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__int128_t shift_right (__int128_t a, __uint128_t b)
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{
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return a >> b;
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}
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__attribute__((noinline))
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__int128_t shift_left (__int128_t a, __uint128_t b)
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{
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return a << b;
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}
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int main ()
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{
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int i, result_int;
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@ -102,7 +114,7 @@ int main ()
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#endif
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}
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arg1 = 3;
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arg1 = vec_result[0];
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uarg2 = 4;
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expected_result = arg1*16;
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@ -186,7 +198,7 @@ int main ()
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#endif
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}
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arg1 = 48;
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arg1 = vec_uresult[0];
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uarg2 = 4;
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expected_result = arg1/16;
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