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Support vec_fmaddsub/vec_fmsubadd for vector HFmode.

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AVX512FP16 supports vfmaddsubXXXph and vfmsubaddXXXph.
Also remove scalar mode from fmaddsub/fmsubadd pattern since there's
no scalar instruction for that.

gcc/ChangeLog:

	PR target/81904
	* config/i386/sse.md (vec_fmaddsub<mode>4): Extend to vector
	HFmode, use mode iterator VFH instead.
	(vec_fmsubadd<mode>4): Ditto.
	(<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>):
	Remove scalar mode from iterator, use VFH_AVX512VL instead.
	(<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>):
	Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr81904.c: New test.
This commit is contained in:
liuhongt 2023-07-31 16:03:45 +08:00
parent 1b446a9760
commit f0b7a61d83
2 changed files with 44 additions and 22 deletions
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44
gcc/config/i386/sse.md
View file

@ -5803,21 +5803,21 @@
;; But this doesn't seem useful in practice.
(define_expand "vec_fmaddsub<mode>4"
[(set (match_operand:VF 0 "register_operand")
(unspec:VF
[(match_operand:VF 1 "nonimmediate_operand")
(match_operand:VF 2 "nonimmediate_operand")
(match_operand:VF 3 "nonimmediate_operand")]
[(set (match_operand:VFH 0 "register_operand")
(unspec:VFH
[(match_operand:VFH 1 "nonimmediate_operand")
(match_operand:VFH 2 "nonimmediate_operand")
(match_operand:VFH 3 "nonimmediate_operand")]
UNSPEC_FMADDSUB))]
"TARGET_FMA || TARGET_FMA4 || (<MODE_SIZE> == 64 || TARGET_AVX512VL)")
(define_expand "vec_fmsubadd<mode>4"
[(set (match_operand:VF 0 "register_operand")
(unspec:VF
[(match_operand:VF 1 "nonimmediate_operand")
(match_operand:VF 2 "nonimmediate_operand")
(neg:VF
(match_operand:VF 3 "nonimmediate_operand"))]
[(set (match_operand:VFH 0 "register_operand")
(unspec:VFH
[(match_operand:VFH 1 "nonimmediate_operand")
(match_operand:VFH 2 "nonimmediate_operand")
(neg:VFH
(match_operand:VFH 3 "nonimmediate_operand"))]
UNSPEC_FMADDSUB))]
"TARGET_FMA || TARGET_FMA4 || (<MODE_SIZE> == 64 || TARGET_AVX512VL)")
@ -5877,11 +5877,11 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"
[(set (match_operand:VFH_SF_AVX512VL 0 "register_operand" "=v,v,v")
(unspec:VFH_SF_AVX512VL
[(match_operand:VFH_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
(match_operand:VFH_SF_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>")
(match_operand:VFH_SF_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>,0")]
[(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v,v")
(unspec:VFH_AVX512VL
[(match_operand:VFH_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
(match_operand:VFH_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>")
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>,0")]
UNSPEC_FMADDSUB))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
@ -5943,12 +5943,12 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"
[(set (match_operand:VFH_SF_AVX512VL 0 "register_operand" "=v,v,v")
(unspec:VFH_SF_AVX512VL
[(match_operand:VFH_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
(match_operand:VFH_SF_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>")
(neg:VFH_SF_AVX512VL
(match_operand:VFH_SF_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>,0"))]
[(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v,v")
(unspec:VFH_AVX512VL
[(match_operand:VFH_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
(match_operand:VFH_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>")
(neg:VFH_AVX512VL
(match_operand:VFH_AVX512VL 3 "<round_nimm_predicate>" "v,<round_constraint>,0"))]
UNSPEC_FMADDSUB))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@

22
gcc/testsuite/gcc.target/i386/pr81904.c Normal file
View file

@ -0,0 +1,22 @@
/* { dg-do compile } */
/* { dg-options "-mavx512fp16 -mavx512vl -O2 -mprefer-vector-width=512" } */
/* { dg-final { scan-assembler-times "vfmaddsub...ph\[ \t\]+\[^\n\]*%zmm\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "vfmsubadd...ph\[ \t\]+\[^\n\]*%zmm\[0-9\]" 1 } } */
void vec_fmaddsub_fp16(int n, _Float16 da_r, _Float16 *x, _Float16* y, _Float16* __restrict z)
{
for (int i = 0; i < 32; i += 2)
{
z[i] = da_r * x[i] - y[i];
z[i+1] = da_r * x[i+1] + y[i+1];
}
}
void vec_fmasubadd_fp16(int n, _Float16 da_r, _Float16 *x, _Float16* y, _Float16* __restrict z)
{
for (int i = 0; i < 32; i += 2)
{
z[i] = da_r * x[i] + y[i];
z[i+1] = da_r * x[i+1] - y[i+1];
}
}