RS6000 add 128-bit Integer Operations part 1
2021-06-07 Carl Love <cel@us.ibm.com> gcc/ChangeLog * config/rs6000/altivec.h (vec_dive, vec_mod): Add define for new builtins. * config/rs6000/altivec.md (UNSPEC_VMULEUD, UNSPEC_VMULESD, UNSPEC_VMULOUD, UNSPEC_VMULOSD): New unspecs. (altivec_eqv1ti, altivec_gtv1ti, altivec_gtuv1ti, altivec_vmuleud, altivec_vmuloud, altivec_vmulesd, altivec_vmulosd, altivec_vrlq, altivec_vrlqmi, altivec_vrlqmi_inst, altivec_vrlqnm, altivec_vrlqnm_inst, altivec_vslq, altivec_vsrq, altivec_vsraq, altivec_vcmpequt_p, altivec_vcmpgtst_p, altivec_vcmpgtut_p): New define_insn. (vec_widen_umult_even_v2di, vec_widen_smult_even_v2di, vec_widen_umult_odd_v2di, vec_widen_smult_odd_v2di, altivec_vrlqmi, altivec_vrlqnm): New define_expands. * config/rs6000/rs6000-builtin.def (VCMPEQUT_P, VCMPGTST_P, VCMPGTUT_P): Add macro expansions. (BU_P10V_AV_P): Add builtin predicate definition. (VCMPGTUT, VCMPGTST, VCMPEQUT, CMPNET, CMPGE_1TI, CMPGE_U1TI, CMPLE_1TI, CMPLE_U1TI, VNOR_V1TI_UNS, VNOR_V1TI, VCMPNET_P, VCMPAET_P, VMULEUD, VMULESD, VMULOUD, VMULOSD, VRLQ, VSLQ, VSRQ, VSRAQ, VRLQNM, DIV_V1TI, UDIV_V1TI, DIVES_V1TI, DIVEU_V1TI, MODS_V1TI, MODU_V1TI, VRLQMI): New macro expansions. (VRLQ, VSLQ, VSRQ, VSRAQ, DIVE, MOD): New overload expansions. * config/rs6000/rs6000-call.c (P10_BUILTIN_VCMPEQUT, P10V_BUILTIN_CMPGE_1TI, P10V_BUILTIN_CMPGE_U1TI, P10V_BUILTIN_VCMPGTUT, P10V_BUILTIN_VCMPGTST, P10V_BUILTIN_CMPLE_1TI, P10V_BUILTIN_VCMPLE_U1TI, P10V_BUILTIN_DIV_V1TI, P10V_BUILTIN_UDIV_V1TI, P10V_BUILTIN_VMULESD, P10V_BUILTIN_VMULEUD, P10V_BUILTIN_VMULOSD, P10V_BUILTIN_VMULOUD, P10V_BUILTIN_VNOR_V1TI, P10V_BUILTIN_VNOR_V1TI_UNS, P10V_BUILTIN_VRLQ, P10V_BUILTIN_VRLQMI, P10V_BUILTIN_VRLQNM, P10V_BUILTIN_VSLQ, P10V_BUILTIN_VSRQ, P10V_BUILTIN_VSRAQ, P10V_BUILTIN_VCMPGTUT_P, P10V_BUILTIN_VCMPGTST_P, P10V_BUILTIN_VCMPEQUT_P, P10V_BUILTIN_VCMPGTUT_P, P10V_BUILTIN_VCMPGTST_P, P10V_BUILTIN_CMPNET, P10V_BUILTIN_VCMPNET_P, P10V_BUILTIN_VCMPAET_P, P10V_BUILTIN_DIVES_V1TI, P10V_BUILTIN_MODS_V1TI, P10V_BUILTIN_MODU_V1TI): New overloaded definitions. (rs6000_gimple_fold_builtin) [P10V_BUILTIN_VCMPEQUT, P10V_BUILTIN_CMPNET, P10V_BUILTIN_CMPGE_1TI, P10V_BUILTIN_CMPGE_U1TI, P10V_BUILTIN_VCMPGTUT, P10V_BUILTIN_VCMPGTST, P10V_BUILTIN_CMPLE_1TI, P10V_BUILTIN_CMPLE_U1TI]: New case statements. (rs6000_init_builtins) [bool_V1TI_type_node, int_ftype_int_v1ti_v1ti]: New assignments. (altivec_init_builtins): New E_V1TImode case statement. (builtin_function_type)[P10_BUILTIN_128BIT_VMULEUD, P10_BUILTIN_128BIT_VMULOUD, P10_BUILTIN_128BIT_DIVEU_V1TI, P10_BUILTIN_128BIT_MODU_V1TI, P10_BUILTIN_CMPGE_U1TI, P10_BUILTIN_VCMPGTUT, P10_BUILTIN_VCMPEQUT]: New case statements. * config/rs6000/rs6000.c (rs6000_handle_altivec_attribute) [E_TImode, E_V1TImode]: New case statements. * config/rs6000/rs6000.h (rs6000_builtin_type_index): New enum value RS6000_BTI_bool_V1TI. * config/rs6000/vector.md (vector_gtv1ti,vector_nltv1ti, vector_gtuv1ti, vector_nltuv1ti, vector_ngtv1ti, vector_ngtuv1ti, vector_eq_v1ti_p, vector_ne_v1ti_p, vector_ae_v1ti_p, vector_gt_v1ti_p, vector_gtu_v1ti_p, vrotlv1ti3, vashlv1ti3, vlshrv1ti3, vashrv1ti3): New define_expands. * config/rs6000/vsx.md (UNSPEC_VSX_DIVSQ, UNSPEC_VSX_DIVUQ, UNSPEC_VSX_DIVESQ, UNSPEC_VSX_DIVEUQ, UNSPEC_VSX_MODSQ, UNSPEC_VSX_MODUQ): New unspecs. (mulv2di3, vsx_div_v1ti, vsx_udiv_v1ti, vsx_dives_v1ti, vsx_diveu_v1ti, vsx_mods_v1ti, vsx_modu_v1ti, xxswapd_v1ti): New define_insns. (vcmpnet): New define_expand. * doc/extend.texi: Add documentation for the new builtins vec_rl, vec_rlmi, vec_rlnm, vec_sl, vec_sr, vec_sra, vec_mule, vec_mulo, vec_div, vec_dive, vec_mod, vec_cmpeq, vec_cmpne, vec_cmpgt, vec_cmplt, vec_cmpge, vec_cmple, vec_all_eq, vec_all_ne, vec_all_gt, vec_all_lt, vec_all_ge, vec_all_le, vec_any_eq, vec_any_ne, vec_any_gt, vec_any_lt, vec_any_ge, vec_any_le. gcc/testsuite/ChangeLog * gcc.target/powerpc/int_128bit-runnable.c: New test file.
This commit is contained in:
Carl Love
parent
2142e34340
commit
f03122f2a7
10 changed files with 3136 additions and 3 deletions
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@ -715,6 +715,9 @@ __altivec_scalar_pred(vec_any_nle,
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#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
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#ifdef _ARCH_PWR10
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#define vec_dive __builtin_vec_dive
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#define vec_mod __builtin_vec_mod
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/* May modify these macro definitions if future capabilities overload
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with support for different vector argument and result types. */
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#define vec_cntlzm(a, b) __builtin_altivec_vclzdm (a, b)
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@ -39,12 +39,16 @@
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UNSPEC_VMULESH
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UNSPEC_VMULEUW
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UNSPEC_VMULESW
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UNSPEC_VMULEUD
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UNSPEC_VMULESD
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UNSPEC_VMULOUB
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UNSPEC_VMULOSB
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UNSPEC_VMULOUH
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UNSPEC_VMULOSH
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UNSPEC_VMULOUW
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UNSPEC_VMULOSW
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UNSPEC_VMULOUD
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UNSPEC_VMULOSD
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UNSPEC_VPKPX
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UNSPEC_VPACK_SIGN_SIGN_SAT
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UNSPEC_VPACK_SIGN_UNS_SAT
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@ -619,6 +623,14 @@
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"vcmpbfp %0,%1,%2"
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[(set_attr "type" "veccmp")])
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(define_insn "altivec_eqv1ti"
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[(set (match_operand:V1TI 0 "altivec_register_operand" "=v")
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(eq:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v")
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(match_operand:V1TI 2 "altivec_register_operand" "v")))]
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"TARGET_POWER10"
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"vcmpequq %0,%1,%2"
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[(set_attr "type" "veccmpfx")])
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(define_insn "altivec_eq<mode>"
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[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
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(eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")
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@ -635,6 +647,14 @@
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"vcmpgts<VI_char> %0,%1,%2"
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[(set_attr "type" "veccmpfx")])
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(define_insn "*altivec_gtv1ti"
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[(set (match_operand:V1TI 0 "altivec_register_operand" "=v")
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(gt:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v")
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(match_operand:V1TI 2 "altivec_register_operand" "v")))]
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"TARGET_POWER10"
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"vcmpgtsq %0,%1,%2"
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[(set_attr "type" "veccmpfx")])
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(define_insn "*altivec_gtu<mode>"
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[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
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(gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v")
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@ -643,6 +663,14 @@
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"vcmpgtu<VI_char> %0,%1,%2"
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[(set_attr "type" "veccmpfx")])
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(define_insn "*altivec_gtuv1ti"
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[(set (match_operand:V1TI 0 "altivec_register_operand" "=v")
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(gtu:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v")
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(match_operand:V1TI 2 "altivec_register_operand" "v")))]
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"TARGET_POWER10"
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"vcmpgtuq %0,%1,%2"
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[(set_attr "type" "veccmpfx")])
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(define_insn "*altivec_eqv4sf"
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[(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
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(eq:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
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@ -1693,6 +1721,19 @@
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DONE;
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})
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(define_expand "vec_widen_umult_even_v2di"
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[(use (match_operand:V1TI 0 "register_operand"))
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(use (match_operand:V2DI 1 "register_operand"))
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(use (match_operand:V2DI 2 "register_operand"))]
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"TARGET_POWER10"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_altivec_vmuleud (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_altivec_vmuloud (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_expand "vec_widen_smult_even_v4si"
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[(use (match_operand:V2DI 0 "register_operand"))
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(use (match_operand:V4SI 1 "register_operand"))
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@ -1706,6 +1747,19 @@
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DONE;
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})
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(define_expand "vec_widen_smult_even_v2di"
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[(use (match_operand:V1TI 0 "register_operand"))
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(use (match_operand:V2DI 1 "register_operand"))
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(use (match_operand:V2DI 2 "register_operand"))]
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"TARGET_POWER10"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_altivec_vmulesd (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_altivec_vmulosd (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_expand "vec_widen_umult_odd_v16qi"
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[(use (match_operand:V8HI 0 "register_operand"))
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(use (match_operand:V16QI 1 "register_operand"))
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@ -1771,6 +1825,19 @@
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DONE;
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})
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(define_expand "vec_widen_umult_odd_v2di"
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[(use (match_operand:V1TI 0 "register_operand"))
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(use (match_operand:V2DI 1 "register_operand"))
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(use (match_operand:V2DI 2 "register_operand"))]
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"TARGET_POWER10"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_altivec_vmuloud (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_altivec_vmuleud (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_expand "vec_widen_smult_odd_v4si"
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[(use (match_operand:V2DI 0 "register_operand"))
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(use (match_operand:V4SI 1 "register_operand"))
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@ -1784,6 +1851,19 @@
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DONE;
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})
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(define_expand "vec_widen_smult_odd_v2di"
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[(use (match_operand:V1TI 0 "register_operand"))
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(use (match_operand:V2DI 1 "register_operand"))
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(use (match_operand:V2DI 2 "register_operand"))]
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"TARGET_POWER10"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_altivec_vmulosd (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_altivec_vmulesd (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "altivec_vmuleub"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
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@ -1865,6 +1945,15 @@
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"vmuleuw %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmuleud"
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[(set (match_operand:V1TI 0 "register_operand" "=v")
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(unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v")
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(match_operand:V2DI 2 "register_operand" "v")]
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UNSPEC_VMULEUD))]
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"TARGET_POWER10"
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"vmuleud %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmulouw"
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[(set (match_operand:V2DI 0 "register_operand" "=v")
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(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
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@ -1874,6 +1963,15 @@
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"vmulouw %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmuloud"
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[(set (match_operand:V1TI 0 "register_operand" "=v")
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(unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v")
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(match_operand:V2DI 2 "register_operand" "v")]
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UNSPEC_VMULOUD))]
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"TARGET_POWER10"
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"vmuloud %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmulesw"
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[(set (match_operand:V2DI 0 "register_operand" "=v")
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(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
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@ -1883,6 +1981,15 @@
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"vmulesw %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmulesd"
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[(set (match_operand:V1TI 0 "register_operand" "=v")
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(unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v")
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(match_operand:V2DI 2 "register_operand" "v")]
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UNSPEC_VMULESD))]
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"TARGET_POWER10"
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"vmulesd %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmulosw"
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[(set (match_operand:V2DI 0 "register_operand" "=v")
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(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
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@ -1892,6 +1999,15 @@
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"vmulosw %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_insn "altivec_vmulosd"
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[(set (match_operand:V1TI 0 "register_operand" "=v")
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(unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v")
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(match_operand:V2DI 2 "register_operand" "v")]
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UNSPEC_VMULOSD))]
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"TARGET_POWER10"
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"vmulosd %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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;; Vector pack/unpack
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(define_insn "altivec_vpkpx"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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@ -1985,6 +2101,15 @@
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"vrl<VI_char> %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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(define_insn "altivec_vrlq"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
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(rotate:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
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(match_operand:V1TI 2 "vsx_register_operand" "v")))]
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"TARGET_POWER10"
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;; rotate amount in needs to be in bits[57:63] of operand2.
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"vrlq %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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(define_insn "altivec_vrl<VI_char>mi"
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[(set (match_operand:VIlong 0 "register_operand" "=v")
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(unspec:VIlong [(match_operand:VIlong 1 "register_operand" "v")
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@ -1995,6 +2120,34 @@
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"vrl<VI_char>mi %0,%1,%3"
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[(set_attr "type" "veclogical")])
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(define_expand "altivec_vrlqmi"
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[(set (match_operand:V1TI 0 "vsx_register_operand")
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(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand")
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(match_operand:V1TI 2 "vsx_register_operand")
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(match_operand:V1TI 3 "vsx_register_operand")]
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UNSPEC_VRLMI))]
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"TARGET_POWER10"
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{
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/* Mask bit begin, end fields need to be in bits [41:55] of 128-bit operand2.
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Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */
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rtx tmp = gen_reg_rtx (V1TImode);
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emit_insn (gen_xxswapd_v1ti (tmp, operands[3]));
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emit_insn (gen_altivec_vrlqmi_inst (operands[0], operands[1], operands[2],
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tmp));
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DONE;
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})
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(define_insn "altivec_vrlqmi_inst"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
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(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
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(match_operand:V1TI 2 "vsx_register_operand" "0")
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(match_operand:V1TI 3 "vsx_register_operand" "v")]
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UNSPEC_VRLMI))]
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"TARGET_POWER10"
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"vrlqmi %0,%1,%3"
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[(set_attr "type" "veclogical")])
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(define_insn "altivec_vrl<VI_char>nm"
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[(set (match_operand:VIlong 0 "register_operand" "=v")
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(unspec:VIlong [(match_operand:VIlong 1 "register_operand" "v")
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@ -2004,6 +2157,31 @@
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"vrl<VI_char>nm %0,%1,%2"
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[(set_attr "type" "veclogical")])
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(define_expand "altivec_vrlqnm"
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[(set (match_operand:V1TI 0 "vsx_register_operand")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand")
|
||||
(match_operand:V1TI 2 "vsx_register_operand")]
|
||||
UNSPEC_VRLNM))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
/* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */
|
||||
rtx tmp = gen_reg_rtx (V1TImode);
|
||||
|
||||
emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
|
||||
emit_insn (gen_altivec_vrlqnm_inst (operands[0], operands[1], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "altivec_vrlqnm_inst"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VRLNM))]
|
||||
"TARGET_POWER10"
|
||||
;; rotate and mask bits need to be in upper 64-bits of operand2.
|
||||
"vrlqnm %0,%1,%2"
|
||||
[(set_attr "type" "veclogical")])
|
||||
|
||||
(define_insn "altivec_vsl"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
||||
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
||||
|
|
@ -2048,6 +2226,15 @@
|
|||
"vsl<VI_char> %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "altivec_vslq"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
/* Shift amount in needs to be in bits[57:63] of 128-bit operand. */
|
||||
"vslq %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "*altivec_vsr<VI_char>"
|
||||
[(set (match_operand:VI2 0 "register_operand" "=v")
|
||||
(lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")
|
||||
|
|
@ -2056,6 +2243,15 @@
|
|||
"vsr<VI_char> %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "altivec_vsrq"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
/* Shift amount in needs to be in bits[57:63] of 128-bit operand. */
|
||||
"vsrq %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "*altivec_vsra<VI_char>"
|
||||
[(set (match_operand:VI2 0 "register_operand" "=v")
|
||||
(ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v")
|
||||
|
|
@ -2064,6 +2260,15 @@
|
|||
"vsra<VI_char> %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "altivec_vsraq"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(ashiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
/* Shift amount in needs to be in bits[57:63] of 128-bit operand. */
|
||||
"vsraq %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "altivec_vsr"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
||||
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
|
||||
|
|
@ -2624,6 +2829,18 @@
|
|||
"vcmpequ<VI_char>. %0,%1,%2"
|
||||
[(set_attr "type" "veccmpfx")])
|
||||
|
||||
(define_insn "altivec_vcmpequt_p"
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand" "v")
|
||||
(match_operand:V1TI 2 "altivec_register_operand" "v"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_operand:V1TI 0 "altivec_register_operand" "=v")
|
||||
(eq:V1TI (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_POWER10"
|
||||
"vcmpequq. %0,%1,%2"
|
||||
[(set_attr "type" "veccmpfx")])
|
||||
|
||||
(define_insn "*altivec_vcmpgts<VI_char>_p"
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")
|
||||
|
|
@ -2636,6 +2853,18 @@
|
|||
"vcmpgts<VI_char>. %0,%1,%2"
|
||||
[(set_attr "type" "veccmpfx")])
|
||||
|
||||
(define_insn "*altivec_vcmpgtst_p"
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(gt:CC (match_operand:V1TI 1 "register_operand" "v")
|
||||
(match_operand:V1TI 2 "register_operand" "v"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_operand:V1TI 0 "register_operand" "=v")
|
||||
(gt:V1TI (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_POWER10"
|
||||
"vcmpgtsq. %0,%1,%2"
|
||||
[(set_attr "type" "veccmpfx")])
|
||||
|
||||
(define_insn "*altivec_vcmpgtu<VI_char>_p"
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
|
||||
|
|
@ -2648,6 +2877,18 @@
|
|||
"vcmpgtu<VI_char>. %0,%1,%2"
|
||||
[(set_attr "type" "veccmpfx")])
|
||||
|
||||
(define_insn "*altivec_vcmpgtut_p"
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(gtu:CC (match_operand:V1TI 1 "register_operand" "v")
|
||||
(match_operand:V1TI 2 "register_operand" "v"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_operand:V1TI 0 "register_operand" "=v")
|
||||
(gtu:V1TI (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_POWER10"
|
||||
"vcmpgtuq. %0,%1,%2"
|
||||
[(set_attr "type" "veccmpfx")])
|
||||
|
||||
(define_insn "*altivec_vcmpeqfp_p"
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
|
||||
|
|
|
|||
|
|
@ -1269,6 +1269,15 @@
|
|||
| RS6000_BTC_TERNARY), \
|
||||
CODE_FOR_ ## ICODE) /* ICODE */
|
||||
|
||||
/* See the comment on BU_ALTIVEC_P. */
|
||||
#define BU_P10V_AV_P(ENUM, NAME, ATTR, ICODE) \
|
||||
RS6000_BUILTIN_P (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
|
||||
"__builtin_altivec_" NAME, /* NAME */ \
|
||||
RS6000_BTM_P10, /* MASK */ \
|
||||
(RS6000_BTC_ ## ATTR /* ATTR */ \
|
||||
| RS6000_BTC_PREDICATE), \
|
||||
CODE_FOR_ ## ICODE) /* ICODE */
|
||||
|
||||
#define BU_P10V_AV_X(ENUM, NAME, ATTR) \
|
||||
RS6000_BUILTIN_X (P10_BUILTIN_ ## ENUM, /* ENUM */ \
|
||||
"__builtin_altivec_" NAME, /* NAME */ \
|
||||
|
|
@ -2880,6 +2889,10 @@ BU_P9_OVERLOAD_2 (CMPRB2, "byte_in_either_range")
|
|||
BU_P9_OVERLOAD_2 (CMPEQB, "byte_in_set")
|
||||
|
||||
/* Builtins for scalar instructions added in ISA 3.1 (power10). */
|
||||
BU_P10V_AV_P (VCMPEQUT_P, "vcmpequt_p", CONST, vector_eq_v1ti_p)
|
||||
BU_P10V_AV_P (VCMPGTST_P, "vcmpgtst_p", CONST, vector_gt_v1ti_p)
|
||||
BU_P10V_AV_P (VCMPGTUT_P, "vcmpgtut_p", CONST, vector_gtu_v1ti_p)
|
||||
|
||||
BU_P10_POWERPC64_MISC_2 (CFUGED, "cfuged", CONST, cfuged)
|
||||
BU_P10_POWERPC64_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm)
|
||||
BU_P10_POWERPC64_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm)
|
||||
|
|
@ -2900,7 +2913,36 @@ BU_P10V_VSX_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
|
|||
BU_P10V_VSX_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
|
||||
BU_P10V_VSX_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
|
||||
BU_P10V_VSX_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
|
||||
BU_P10V_AV_2 (VCMPGTUT, "vcmpgtut", CONST, vector_gtuv1ti)
|
||||
BU_P10V_AV_2 (VCMPGTST, "vcmpgtst", CONST, vector_gtv1ti)
|
||||
BU_P10V_AV_2 (VCMPEQUT, "vcmpequt", CONST, eqvv1ti3)
|
||||
BU_P10V_AV_2 (CMPNET, "vcmpnet", CONST, vcmpnet)
|
||||
BU_P10V_AV_2 (CMPGE_1TI, "cmpge_1ti", CONST, vector_nltv1ti)
|
||||
BU_P10V_AV_2 (CMPGE_U1TI, "cmpge_u1ti", CONST, vector_nltuv1ti)
|
||||
BU_P10V_AV_2 (CMPLE_1TI, "cmple_1ti", CONST, vector_ngtv1ti)
|
||||
BU_P10V_AV_2 (CMPLE_U1TI, "cmple_u1ti", CONST, vector_ngtuv1ti)
|
||||
BU_P10V_AV_2 (VNOR_V1TI_UNS, "vnor_v1ti_uns",CONST, norv1ti3)
|
||||
BU_P10V_AV_2 (VNOR_V1TI, "vnor_v1ti", CONST, norv1ti3)
|
||||
BU_P10V_AV_2 (VCMPNET_P, "vcmpnet_p", CONST, vector_ne_v1ti_p)
|
||||
BU_P10V_AV_2 (VCMPAET_P, "vcmpaet_p", CONST, vector_ae_v1ti_p)
|
||||
|
||||
BU_P10V_AV_2 (VMULEUD, "vmuleud", CONST, vec_widen_umult_even_v2di)
|
||||
BU_P10V_AV_2 (VMULESD, "vmulesd", CONST, vec_widen_smult_even_v2di)
|
||||
BU_P10V_AV_2 (VMULOUD, "vmuloud", CONST, vec_widen_umult_odd_v2di)
|
||||
BU_P10V_AV_2 (VMULOSD, "vmulosd", CONST, vec_widen_smult_odd_v2di)
|
||||
BU_P10V_AV_2 (VRLQ, "vrlq", CONST, vrotlv1ti3)
|
||||
BU_P10V_AV_2 (VSLQ, "vslq", CONST, vashlv1ti3)
|
||||
BU_P10V_AV_2 (VSRQ, "vsrq", CONST, vlshrv1ti3)
|
||||
BU_P10V_AV_2 (VSRAQ, "vsraq", CONST, vashrv1ti3)
|
||||
BU_P10V_AV_2 (VRLQNM, "vrlqnm", CONST, altivec_vrlqnm)
|
||||
BU_P10V_AV_2 (DIV_V1TI, "div_1ti", CONST, vsx_div_v1ti)
|
||||
BU_P10V_AV_2 (UDIV_V1TI, "udiv_1ti", CONST, vsx_udiv_v1ti)
|
||||
BU_P10V_AV_2 (DIVES_V1TI, "dives", CONST, vsx_dives_v1ti)
|
||||
BU_P10V_AV_2 (DIVEU_V1TI, "diveu", CONST, vsx_diveu_v1ti)
|
||||
BU_P10V_AV_2 (MODS_V1TI, "mods", CONST, vsx_mods_v1ti)
|
||||
BU_P10V_AV_2 (MODU_V1TI, "modu", CONST, vsx_modu_v1ti)
|
||||
|
||||
BU_P10V_AV_3 (VRLQMI, "vrlqmi", CONST, altivec_vrlqmi)
|
||||
BU_P10V_AV_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
|
||||
BU_P10V_AV_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
|
||||
BU_P10V_AV_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
|
||||
|
|
@ -3025,6 +3067,10 @@ BU_P10_OVERLOAD_2 (CLRR, "clrr")
|
|||
BU_P10_OVERLOAD_2 (GNB, "gnb")
|
||||
BU_P10_OVERLOAD_4 (XXEVAL, "xxeval")
|
||||
BU_P10_OVERLOAD_2 (XXGENPCVM, "xxgenpcvm")
|
||||
BU_P10_OVERLOAD_2 (VRLQ, "vrlq")
|
||||
BU_P10_OVERLOAD_2 (VSLQ, "vslq")
|
||||
BU_P10_OVERLOAD_2 (VSRQ, "vsrq")
|
||||
BU_P10_OVERLOAD_2 (VSRAQ, "vsraq")
|
||||
|
||||
BU_P10_OVERLOAD_3 (EXTRACTL, "extractl")
|
||||
BU_P10_OVERLOAD_3 (EXTRACTH, "extracth")
|
||||
|
|
|
|||
|
|
@ -843,6 +843,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPEQ, P10V_BUILTIN_VCMPEQUT,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPEQ, P10V_BUILTIN_VCMPEQUT,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
|
||||
|
|
@ -889,6 +893,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0},
|
||||
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGE, P10V_BUILTIN_CMPGE_1TI,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0},
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGE, P10V_BUILTIN_CMPGE_U1TI,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0},
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
|
||||
|
|
@ -903,8 +913,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, P10V_BUILTIN_VCMPGTUT,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, P10V_BUILTIN_VCMPGTST,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
|
||||
|
|
@ -947,6 +961,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0},
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPLE, P10V_BUILTIN_CMPLE_1TI,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0},
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPLE, P10V_BUILTIN_CMPLE_U1TI,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0},
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
|
||||
|
|
@ -1086,6 +1105,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIV_V1TI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_UDIV_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
|
||||
{ P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V4SI,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
|
||||
|
|
@ -1097,6 +1121,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V1TI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
|
||||
{ P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V4SI,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
|
||||
|
|
@ -1108,6 +1137,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V1TI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
|
||||
{ VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
|
||||
RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
|
||||
|
|
@ -1973,6 +2007,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MULE, P10V_BUILTIN_VMULESD,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MULE, P10V_BUILTIN_VMULEUD,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
|
||||
|
|
@ -1996,6 +2035,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MULO, P10V_BUILTIN_VMULOSD,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MULO, P10V_BUILTIN_VMULOUD,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
|
||||
|
|
@ -2038,6 +2082,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
|
||||
RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_bool_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_bool_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
|
||||
|
|
@ -2299,6 +2353,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_RL, P10V_BUILTIN_VRLQ,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_RL, P10V_BUILTIN_VRLQ,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
|
||||
|
|
@ -2317,12 +2376,23 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
|
||||
{ P9V_BUILTIN_VEC_RLMI, P10V_BUILTIN_VRLQMI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI },
|
||||
{ P9V_BUILTIN_VEC_RLMI, P10V_BUILTIN_VRLQMI,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
|
||||
{ P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ P9V_BUILTIN_VEC_RLNM, P10V_BUILTIN_VRLQNM,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ P9V_BUILTIN_VEC_RLNM, P10V_BUILTIN_VRLQNM,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
|
||||
|
|
@ -2339,6 +2409,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SL, P10V_BUILTIN_VSLQ,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SL, P10V_BUILTIN_VSLQ,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
|
||||
RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
|
||||
|
|
@ -2535,6 +2610,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SR, P10V_BUILTIN_VSRQ,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SR, P10V_BUILTIN_VSRQ,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
|
||||
|
|
@ -2563,6 +2643,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SRA, P10V_BUILTIN_VSRAQ,
|
||||
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_SRA, P10V_BUILTIN_VSRAQ,
|
||||
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
|
||||
|
|
@ -4180,12 +4265,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, P10V_BUILTIN_VCMPGTUT_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, P10V_BUILTIN_VCMPGTST_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
|
||||
|
|
@ -4250,6 +4339,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P10V_BUILTIN_VCMPEQUT_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P10V_BUILTIN_VCMPEQUT_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
|
||||
|
|
@ -4301,12 +4394,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, P10V_BUILTIN_VCMPGTUT_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, P10V_BUILTIN_VCMPGTST_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
|
||||
|
|
@ -4955,6 +5052,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPNE, P10V_BUILTIN_CMPNET,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI,
|
||||
RS6000_BTI_V1TI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_CMPNE, P10V_BUILTIN_CMPNET,
|
||||
RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V1TI, 0 },
|
||||
|
||||
/* The following 2 entries have been deprecated. */
|
||||
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
|
||||
|
|
@ -5055,6 +5158,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
|
||||
RS6000_BTI_bool_V2DI, 0 },
|
||||
{ P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
|
||||
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
|
||||
|
|
@ -5160,7 +5267,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
{ P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
|
||||
RS6000_BTI_bool_V2DI, 0 },
|
||||
|
||||
{ P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
|
||||
{ P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
|
||||
{ P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
|
||||
RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
|
||||
{ P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
|
||||
|
|
@ -12552,12 +12662,14 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
|
|||
case ALTIVEC_BUILTIN_VCMPEQUH:
|
||||
case ALTIVEC_BUILTIN_VCMPEQUW:
|
||||
case P8V_BUILTIN_VCMPEQUD:
|
||||
case P10V_BUILTIN_VCMPEQUT:
|
||||
fold_compare_helper (gsi, EQ_EXPR, stmt);
|
||||
return true;
|
||||
|
||||
case P9V_BUILTIN_CMPNEB:
|
||||
case P9V_BUILTIN_CMPNEH:
|
||||
case P9V_BUILTIN_CMPNEW:
|
||||
case P10V_BUILTIN_CMPNET:
|
||||
fold_compare_helper (gsi, NE_EXPR, stmt);
|
||||
return true;
|
||||
|
||||
|
|
@ -12569,6 +12681,8 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
|
|||
case VSX_BUILTIN_CMPGE_U4SI:
|
||||
case VSX_BUILTIN_CMPGE_2DI:
|
||||
case VSX_BUILTIN_CMPGE_U2DI:
|
||||
case P10V_BUILTIN_CMPGE_1TI:
|
||||
case P10V_BUILTIN_CMPGE_U1TI:
|
||||
fold_compare_helper (gsi, GE_EXPR, stmt);
|
||||
return true;
|
||||
|
||||
|
|
@ -12580,6 +12694,8 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
|
|||
case ALTIVEC_BUILTIN_VCMPGTUW:
|
||||
case P8V_BUILTIN_VCMPGTUD:
|
||||
case P8V_BUILTIN_VCMPGTSD:
|
||||
case P10V_BUILTIN_VCMPGTUT:
|
||||
case P10V_BUILTIN_VCMPGTST:
|
||||
fold_compare_helper (gsi, GT_EXPR, stmt);
|
||||
return true;
|
||||
|
||||
|
|
@ -12591,6 +12707,8 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
|
|||
case VSX_BUILTIN_CMPLE_U4SI:
|
||||
case VSX_BUILTIN_CMPLE_2DI:
|
||||
case VSX_BUILTIN_CMPLE_U2DI:
|
||||
case P10V_BUILTIN_CMPLE_1TI:
|
||||
case P10V_BUILTIN_CMPLE_U1TI:
|
||||
fold_compare_helper (gsi, LE_EXPR, stmt);
|
||||
return true;
|
||||
|
||||
|
|
@ -13318,6 +13436,8 @@ rs6000_init_builtins (void)
|
|||
? "__vector __bool long"
|
||||
: "__vector __bool long long",
|
||||
bool_long_long_type_node, 2);
|
||||
bool_V1TI_type_node = rs6000_vector_type ("__vector __bool __int128",
|
||||
intTI_type_node, 1);
|
||||
pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
|
||||
pixel_type_node, 8);
|
||||
|
||||
|
|
@ -13515,6 +13635,10 @@ altivec_init_builtins (void)
|
|||
= build_function_type_list (integer_type_node,
|
||||
integer_type_node, V2DI_type_node,
|
||||
V2DI_type_node, NULL_TREE);
|
||||
tree int_ftype_int_v1ti_v1ti
|
||||
= build_function_type_list (integer_type_node,
|
||||
integer_type_node, V1TI_type_node,
|
||||
V1TI_type_node, NULL_TREE);
|
||||
tree void_ftype_v4si
|
||||
= build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
|
||||
tree v8hi_ftype_void
|
||||
|
|
@ -13882,6 +14006,9 @@ altivec_init_builtins (void)
|
|||
case E_VOIDmode:
|
||||
type = int_ftype_int_opaque_opaque;
|
||||
break;
|
||||
case E_V1TImode:
|
||||
type = int_ftype_int_v1ti_v1ti;
|
||||
break;
|
||||
case E_V2DImode:
|
||||
type = int_ftype_int_v2di_v2di;
|
||||
break;
|
||||
|
|
@ -14487,12 +14614,16 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
|
|||
case P10V_BUILTIN_XXGENPCVM_V2DI:
|
||||
case P10V_BUILTIN_DIVEU_V4SI:
|
||||
case P10V_BUILTIN_DIVEU_V2DI:
|
||||
case P10V_BUILTIN_DIVEU_V1TI:
|
||||
case P10V_BUILTIN_DIVU_V4SI:
|
||||
case P10V_BUILTIN_DIVU_V2DI:
|
||||
case P10V_BUILTIN_MODU_V1TI:
|
||||
case P10V_BUILTIN_MODU_V2DI:
|
||||
case P10V_BUILTIN_MODU_V4SI:
|
||||
case P10V_BUILTIN_MULHU_V2DI:
|
||||
case P10V_BUILTIN_MULHU_V4SI:
|
||||
case P10V_BUILTIN_VMULEUD:
|
||||
case P10V_BUILTIN_VMULOUD:
|
||||
h.uns_p[0] = 1;
|
||||
h.uns_p[1] = 1;
|
||||
h.uns_p[2] = 1;
|
||||
|
|
@ -14592,10 +14723,13 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
|
|||
case VSX_BUILTIN_CMPGE_U8HI:
|
||||
case VSX_BUILTIN_CMPGE_U4SI:
|
||||
case VSX_BUILTIN_CMPGE_U2DI:
|
||||
case P10V_BUILTIN_CMPGE_U1TI:
|
||||
case ALTIVEC_BUILTIN_VCMPGTUB:
|
||||
case ALTIVEC_BUILTIN_VCMPGTUH:
|
||||
case ALTIVEC_BUILTIN_VCMPGTUW:
|
||||
case P8V_BUILTIN_VCMPGTUD:
|
||||
case P10V_BUILTIN_VCMPGTUT:
|
||||
case P10V_BUILTIN_VCMPEQUT:
|
||||
h.uns_p[1] = 1;
|
||||
h.uns_p[2] = 1;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -20217,6 +20217,7 @@ rs6000_handle_altivec_attribute (tree *node,
|
|||
case 'b':
|
||||
switch (mode)
|
||||
{
|
||||
case E_TImode: case E_V1TImode: result = bool_V1TI_type_node; break;
|
||||
case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
|
||||
case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
|
||||
case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
|
||||
|
|
|
|||
|
|
@ -2321,7 +2321,6 @@ extern int frame_pointer_needed;
|
|||
#define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */
|
||||
#define RS6000_BTM_P10 MASK_POWER10
|
||||
|
||||
|
||||
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
|
||||
| RS6000_BTM_VSX \
|
||||
| RS6000_BTM_P8_VECTOR \
|
||||
|
|
@ -2434,6 +2433,7 @@ enum rs6000_builtin_type_index
|
|||
RS6000_BTI_bool_V8HI, /* __vector __bool short */
|
||||
RS6000_BTI_bool_V4SI, /* __vector __bool int */
|
||||
RS6000_BTI_bool_V2DI, /* __vector __bool long */
|
||||
RS6000_BTI_bool_V1TI, /* __vector __bool 128-bit */
|
||||
RS6000_BTI_pixel_V8HI, /* __vector __pixel */
|
||||
RS6000_BTI_long, /* long_integer_type_node */
|
||||
RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
|
||||
|
|
@ -2487,6 +2487,7 @@ enum rs6000_builtin_type_index
|
|||
#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
|
||||
#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
|
||||
#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
|
||||
#define bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V1TI])
|
||||
#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
|
||||
|
||||
#define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI KF TF])
|
||||
|
||||
;; Vector comparison modes
|
||||
(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])
|
||||
(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
|
||||
|
||||
;; Vector init/extract modes
|
||||
(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
|
||||
|
|
@ -697,6 +697,17 @@
|
|||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_nltv1ti"
|
||||
[(set (match_operand:V1TI 3 "vlogical_operand")
|
||||
(gt:V1TI (match_operand:V1TI 2 "vlogical_operand")
|
||||
(match_operand:V1TI 1 "vlogical_operand")))
|
||||
(set (match_operand:V1TI 0 "vlogical_operand")
|
||||
(not:V1TI (match_dup 3)))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_gtu<mode>"
|
||||
[(set (match_operand:VEC_I 0 "vint_operand")
|
||||
(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand")
|
||||
|
|
@ -704,6 +715,13 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
(define_expand "vector_gtuv1ti"
|
||||
[(set (match_operand:V1TI 0 "altivec_register_operand")
|
||||
(gtu:V1TI (match_operand:V1TI 1 "altivec_register_operand")
|
||||
(match_operand:V1TI 2 "altivec_register_operand")))]
|
||||
"TARGET_POWER10"
|
||||
"")
|
||||
|
||||
; >= for integer vectors: swap operands and apply not-greater-than
|
||||
(define_expand "vector_nltu<mode>"
|
||||
[(set (match_operand:VEC_I 3 "vlogical_operand")
|
||||
|
|
@ -716,6 +734,17 @@
|
|||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_nltuv1ti"
|
||||
[(set (match_operand:V1TI 3 "vlogical_operand")
|
||||
(gtu:V1TI (match_operand:V1TI 2 "vlogical_operand")
|
||||
(match_operand:V1TI 1 "vlogical_operand")))
|
||||
(set (match_operand:V1TI 0 "vlogical_operand")
|
||||
(not:V1TI (match_dup 3)))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_geu<mode>"
|
||||
[(set (match_operand:VEC_I 0 "vint_operand")
|
||||
(geu:VEC_I (match_operand:VEC_I 1 "vint_operand")
|
||||
|
|
@ -735,6 +764,17 @@
|
|||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_ngtv1ti"
|
||||
[(set (match_operand:V1TI 3 "vlogical_operand")
|
||||
(gt:V1TI (match_operand:V1TI 1 "vlogical_operand")
|
||||
(match_operand:V1TI 2 "vlogical_operand")))
|
||||
(set (match_operand:V1TI 0 "vlogical_operand")
|
||||
(not:V1TI (match_dup 3)))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_ngtu<mode>"
|
||||
[(set (match_operand:VEC_I 3 "vlogical_operand")
|
||||
(gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
|
||||
|
|
@ -746,6 +786,17 @@
|
|||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "vector_ngtuv1ti"
|
||||
[(set (match_operand:V1TI 3 "vlogical_operand")
|
||||
(gtu:V1TI (match_operand:V1TI 1 "vlogical_operand")
|
||||
(match_operand:V1TI 2 "vlogical_operand")))
|
||||
(set (match_operand:V1TI 0 "vlogical_operand")
|
||||
(not:V1TI (match_dup 3)))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
|
||||
})
|
||||
|
||||
; There are 14 possible vector FP comparison operators, gt and eq of them have
|
||||
; been expanded above, so just support 12 remaining operators here.
|
||||
|
||||
|
|
@ -894,6 +945,18 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
(define_expand "vector_eq_v1ti_p"
|
||||
[(parallel
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
|
||||
(match_operand:V1TI 2 "altivec_register_operand"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_operand:V1TI 0 "vlogical_operand")
|
||||
(eq:V1TI (match_dup 1)
|
||||
(match_dup 2)))])]
|
||||
"TARGET_POWER10"
|
||||
"")
|
||||
|
||||
;; This expansion handles the V16QI, V8HI, and V4SI modes in the
|
||||
;; implementation of the vec_all_ne built-in functions on Power9.
|
||||
(define_expand "vector_ne_<mode>_p"
|
||||
|
|
@ -976,6 +1039,23 @@
|
|||
operands[3] = gen_reg_rtx (V2DImode);
|
||||
})
|
||||
|
||||
(define_expand "vector_ne_v1ti_p"
|
||||
[(parallel
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
|
||||
(match_operand:V1TI 2 "altivec_register_operand"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_dup 3)
|
||||
(eq:V1TI (match_dup 1)
|
||||
(match_dup 2)))])
|
||||
(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(eq:SI (reg:CC CR6_REGNO)
|
||||
(const_int 0)))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (V1TImode);
|
||||
})
|
||||
|
||||
;; This expansion handles the V2DI mode in the implementation of the
|
||||
;; vec_any_eq built-in function on Power9.
|
||||
;;
|
||||
|
|
@ -1002,6 +1082,26 @@
|
|||
operands[3] = gen_reg_rtx (V2DImode);
|
||||
})
|
||||
|
||||
(define_expand "vector_ae_v1ti_p"
|
||||
[(parallel
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(eq:CC (match_operand:V1TI 1 "altivec_register_operand")
|
||||
(match_operand:V1TI 2 "altivec_register_operand"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_dup 3)
|
||||
(eq:V1TI (match_dup 1)
|
||||
(match_dup 2)))])
|
||||
(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(eq:SI (reg:CC CR6_REGNO)
|
||||
(const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(xor:SI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (V1TImode);
|
||||
})
|
||||
|
||||
;; This expansion handles the V4SF and V2DF modes in the Power9
|
||||
;; implementation of the vec_all_ne built-in functions. Note that the
|
||||
;; expansions for this pattern with these modes makes no use of power9-
|
||||
|
|
@ -1061,6 +1161,18 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
(define_expand "vector_gt_v1ti_p"
|
||||
[(parallel
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(gt:CC (match_operand:V1TI 1 "vlogical_operand")
|
||||
(match_operand:V1TI 2 "vlogical_operand"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_operand:V1TI 0 "vlogical_operand")
|
||||
(gt:V1TI (match_dup 1)
|
||||
(match_dup 2)))])]
|
||||
"TARGET_POWER10"
|
||||
"")
|
||||
|
||||
(define_expand "vector_ge_<mode>_p"
|
||||
[(parallel
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
|
|
@ -1085,6 +1197,18 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
(define_expand "vector_gtu_v1ti_p"
|
||||
[(parallel
|
||||
[(set (reg:CC CR6_REGNO)
|
||||
(unspec:CC [(gtu:CC (match_operand:V1TI 1 "altivec_register_operand")
|
||||
(match_operand:V1TI 2 "altivec_register_operand"))]
|
||||
UNSPEC_PREDICATE))
|
||||
(set (match_operand:V1TI 0 "altivec_register_operand")
|
||||
(gtu:V1TI (match_dup 1)
|
||||
(match_dup 2)))])]
|
||||
"TARGET_POWER10"
|
||||
"")
|
||||
|
||||
;; AltiVec/VSX predicates.
|
||||
|
||||
;; This expansion is triggered during expansion of predicate built-in
|
||||
|
|
@ -1460,6 +1584,20 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
(define_expand "vrotlv1ti3"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(rotate:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
/* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */
|
||||
rtx tmp = gen_reg_rtx (V1TImode);
|
||||
|
||||
emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
|
||||
emit_insn (gen_altivec_vrlq (operands[0], operands[1], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Expanders for rotatert to make use of vrotl
|
||||
(define_expand "vrotr<mode>3"
|
||||
[(set (match_operand:VEC_I 0 "vint_operand")
|
||||
|
|
@ -1481,6 +1619,21 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
;; No immediate version of this 128-bit instruction
|
||||
(define_expand "vashlv1ti3"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
/* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */
|
||||
rtx tmp = gen_reg_rtx (V1TImode);
|
||||
|
||||
emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
|
||||
emit_insn (gen_altivec_vslq (operands[0], operands[1], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Expanders for logical shift right on each vector element
|
||||
(define_expand "vlshr<mode>3"
|
||||
[(set (match_operand:VEC_I 0 "vint_operand")
|
||||
|
|
@ -1489,6 +1642,21 @@
|
|||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
;; No immediate version of this 128-bit instruction
|
||||
(define_expand "vlshrv1ti3"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
/* Shift amount in needs to be put into bits[57:63] of 128-bit operand2. */
|
||||
rtx tmp = gen_reg_rtx (V1TImode);
|
||||
|
||||
emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
|
||||
emit_insn (gen_altivec_vsrq (operands[0], operands[1], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Expanders for arithmetic shift right on each vector element
|
||||
(define_expand "vashr<mode>3"
|
||||
[(set (match_operand:VEC_I 0 "vint_operand")
|
||||
|
|
@ -1496,6 +1664,22 @@
|
|||
(match_operand:VEC_I 2 "vint_operand")))]
|
||||
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
|
||||
"")
|
||||
|
||||
;; No immediate version of this 128-bit instruction
|
||||
(define_expand "vashrv1ti3"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(ashiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
/* Shift amount in needs to be put into bits[57:63] of 128-bit operand2. */
|
||||
rtx tmp = gen_reg_rtx (V1TImode);
|
||||
|
||||
emit_insn (gen_xxswapd_v1ti (tmp, operands[2]));
|
||||
emit_insn (gen_altivec_vsraq (operands[0], operands[1], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
||||
;; Vector reduction expanders for VSX
|
||||
; The (VEC_reduc:...
|
||||
|
|
|
|||
|
|
@ -302,6 +302,12 @@
|
|||
UNSPEC_VSX_XXSPLTD
|
||||
UNSPEC_VSX_DIVSD
|
||||
UNSPEC_VSX_DIVUD
|
||||
UNSPEC_VSX_DIVSQ
|
||||
UNSPEC_VSX_DIVUQ
|
||||
UNSPEC_VSX_DIVESQ
|
||||
UNSPEC_VSX_DIVEUQ
|
||||
UNSPEC_VSX_MODSQ
|
||||
UNSPEC_VSX_MODUQ
|
||||
UNSPEC_VSX_MULSD
|
||||
UNSPEC_VSX_SIGN_EXTEND
|
||||
UNSPEC_VSX_XVCVBF16SPN
|
||||
|
|
@ -1781,6 +1787,61 @@
|
|||
}
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
;; Vector integer signed/unsigned divide
|
||||
(define_insn "vsx_div_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VSX_DIVSQ))]
|
||||
"TARGET_POWER10"
|
||||
"vdivsq %0,%1,%2"
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
(define_insn "vsx_udiv_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VSX_DIVUQ))]
|
||||
"TARGET_POWER10"
|
||||
"vdivuq %0,%1,%2"
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
(define_insn "vsx_dives_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VSX_DIVESQ))]
|
||||
"TARGET_POWER10"
|
||||
"vdivesq %0,%1,%2"
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
(define_insn "vsx_diveu_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VSX_DIVEUQ))]
|
||||
"TARGET_POWER10"
|
||||
"vdiveuq %0,%1,%2"
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
(define_insn "vsx_mods_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VSX_MODSQ))]
|
||||
"TARGET_POWER10"
|
||||
"vmodsq %0,%1,%2"
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
(define_insn "vsx_modu_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v")
|
||||
(match_operand:V1TI 2 "vsx_register_operand" "v")]
|
||||
UNSPEC_VSX_MODUQ))]
|
||||
"TARGET_POWER10"
|
||||
"vmoduq %0,%1,%2"
|
||||
[(set_attr "type" "div")])
|
||||
|
||||
;; *tdiv* instruction returning the FG flag
|
||||
(define_expand "vsx_tdiv<mode>3_fg"
|
||||
[(set (match_dup 3)
|
||||
|
|
@ -3126,6 +3187,21 @@
|
|||
"xxpermdi %x0,%x1,%x1,2"
|
||||
[(set_attr "type" "vecperm")])
|
||||
|
||||
;; Swap upper/lower 64-bit values in a 128-bit vector
|
||||
(define_insn "xxswapd_v1ti"
|
||||
[(set (match_operand:V1TI 0 "vsx_register_operand" "=v")
|
||||
(subreg:V1TI
|
||||
(vec_select:V2DI
|
||||
(subreg:V2DI
|
||||
(match_operand:V1TI 1 "vsx_register_operand" "v") 0 )
|
||||
(parallel [(const_int 1)(const_int 0)]))
|
||||
0))]
|
||||
"TARGET_POWER10"
|
||||
;; AIX does not support extended mnemonic xxswapd. Use the basic
|
||||
;; mnemonic xxpermdi instead.
|
||||
"xxpermdi %x0,%x1,%x1,2"
|
||||
[(set_attr "type" "vecperm")])
|
||||
|
||||
(define_insn "xxgenpcvm_<mode>_internal"
|
||||
[(set (match_operand:VSX_EXTRACT_I4 0 "altivec_register_operand" "=wa")
|
||||
(unspec:VSX_EXTRACT_I4
|
||||
|
|
@ -5525,6 +5601,19 @@
|
|||
"vcmpneb %0,%1,%2"
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
;; Vector Compare Not Equal v1ti (specified/not+eq:)
|
||||
(define_expand "vcmpnet"
|
||||
[(set (match_operand:V1TI 0 "altivec_register_operand")
|
||||
(not:V1TI
|
||||
(eq:V1TI (match_operand:V1TI 1 "altivec_register_operand")
|
||||
(match_operand:V1TI 2 "altivec_register_operand"))))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
emit_insn (gen_eqvv1ti3 (operands[0], operands[1], operands[2]));
|
||||
emit_insn (gen_one_cmplv1ti2 (operands[0], operands[0]));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Vector Compare Not Equal or Zero Byte
|
||||
(define_insn "vcmpnezb"
|
||||
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
|
||||
|
|
|
|||
|
|
@ -20174,6 +20174,177 @@ Generate PCV from specified Mask size, as if implemented by the
|
|||
immediate value is either 0, 1, 2 or 3.
|
||||
@findex vec_genpcvm
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_rl (vector unsigned __int128 A,
|
||||
vector unsigned __int128 B);
|
||||
@exdent vector signed __int128 vec_rl (vector signed __int128 A,
|
||||
vector unsigned __int128 B);
|
||||
@end smallexample
|
||||
|
||||
Result value: Each element of R is obtained by rotating the corresponding element
|
||||
of A left by the number of bits specified by the corresponding element of B.
|
||||
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_rlmi (vector unsigned __int128,
|
||||
vector unsigned __int128,
|
||||
vector unsigned __int128);
|
||||
@exdent vector signed __int128 vec_rlmi (vector signed __int128,
|
||||
vector signed __int128,
|
||||
vector unsigned __int128);
|
||||
@end smallexample
|
||||
|
||||
Returns the result of rotating the first input and inserting it under mask
|
||||
into the second input. The first bit in the mask, the last bit in the mask are
|
||||
obtained from the two 7-bit fields bits [108:115] and bits [117:123]
|
||||
respectively of the second input. The shift is obtained from the third input
|
||||
in the 7-bit field [125:131] where all bits counted from zero at the left.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_rlnm (vector unsigned __int128,
|
||||
vector unsigned __int128,
|
||||
vector unsigned __int128);
|
||||
@exdent vector signed __int128 vec_rlnm (vector signed __int128,
|
||||
vector unsigned __int128,
|
||||
vector unsigned __int128);
|
||||
@end smallexample
|
||||
|
||||
Returns the result of rotating the first input and ANDing it with a mask. The
|
||||
first bit in the mask and the last bit in the mask are obtained from the two
|
||||
7-bit fields bits [117:123] and bits [125:131] respectively of the second
|
||||
input. The shift is obtained from the third input in the 7-bit field bits
|
||||
[125:131] where all bits counted from zero at the left.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_sl(vector unsigned __int128 A, vector unsigned __int128 B);
|
||||
@exdent vector signed __int128 vec_sl(vector signed __int128 A, vector unsigned __int128 B);
|
||||
@end smallexample
|
||||
|
||||
Result value: Each element of R is obtained by shifting the corresponding element of
|
||||
A left by the number of bits specified by the corresponding element of B.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_sr(vector unsigned __int128 A, vector unsigned __int128 B);
|
||||
@exdent vector signed __int128 vec_sr(vector signed __int128 A, vector unsigned __int128 B);
|
||||
@end smallexample
|
||||
|
||||
Result value: Each element of R is obtained by shifting the corresponding element of
|
||||
A right by the number of bits specified by the corresponding element of B.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_sra(vector unsigned __int128 A, vector unsigned __int128 B);
|
||||
@exdent vector signed __int128 vec_sra(vector signed __int128 A, vector unsigned __int128 B);
|
||||
@end smallexample
|
||||
|
||||
Result value: Each element of R is obtained by arithmetic shifting the corresponding
|
||||
element of A right by the number of bits specified by the corresponding element of B.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_mule (vector unsigned long long,
|
||||
vector unsigned long long);
|
||||
@exdent vector signed __int128 vec_mule (vector signed long long,
|
||||
vector signed long long);
|
||||
@end smallexample
|
||||
|
||||
Returns a vector containing a 128-bit integer result of multiplying the even
|
||||
doubleword elements of the two inputs.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_mulo (vector unsigned long long,
|
||||
vector unsigned long long);
|
||||
@exdent vector signed __int128 vec_mulo (vector signed long long,
|
||||
vector signed long long);
|
||||
@end smallexample
|
||||
|
||||
Returns a vector containing a 128-bit integer result of multiplying the odd
|
||||
doubleword elements of the two inputs.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_div (vector unsigned __int128,
|
||||
vector unsigned __int128);
|
||||
@exdent vector signed __int128 vec_div (vector signed __int128,
|
||||
vector signed __int128);
|
||||
@end smallexample
|
||||
|
||||
Returns the result of dividing the first operand by the second operand. An
|
||||
attempt to divide any value by zero or to divide the most negative signed
|
||||
128-bit integer by negative one results in an undefined value.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_dive (vector unsigned __int128,
|
||||
vector unsigned __int128);
|
||||
@exdent vector signed __int128 vec_dive (vector signed __int128,
|
||||
vector signed __int128);
|
||||
@end smallexample
|
||||
|
||||
The result is produced by shifting the first input left by 128 bits and
|
||||
dividing by the second. If an attempt is made to divide by zero or the result
|
||||
is larger than 128 bits, the result is undefined.
|
||||
|
||||
@smallexample
|
||||
@exdent vector unsigned __int128 vec_mod (vector unsigned __int128,
|
||||
vector unsigned __int128);
|
||||
@exdent vector signed __int128 vec_mod (vector signed __int128,
|
||||
vector signed __int128);
|
||||
@end smallexample
|
||||
|
||||
The result is the modulo result of dividing the first input by the second
|
||||
input.
|
||||
|
||||
The following builtins perform 128-bit vector comparisons. The
|
||||
@code{vec_all_xx}, @code{vec_any_xx}, and @code{vec_cmpxx}, where @code{xx} is
|
||||
one of the operations @code{eq, ne, gt, lt, ge, le} perform pairwise
|
||||
comparisons between the elements at the same positions within their two vector
|
||||
arguments. The @code{vec_all_xx}function returns a non-zero value if and only
|
||||
if all pairwise comparisons are true. The @code{vec_any_xx} function returns
|
||||
a non-zero value if and only if at least one pairwise comparison is true. The
|
||||
@code{vec_cmpxx}function returns a vector of the same type as its two
|
||||
arguments, within which each element consists of all ones to denote that
|
||||
specified logical comparison of the corresponding elements was true.
|
||||
Otherwise, the element of the returned vector contains all zeros.
|
||||
|
||||
@smallexample
|
||||
vector bool __int128 vec_cmpeq (vector signed __int128, vector signed __int128);
|
||||
vector bool __int128 vec_cmpeq (vector unsigned __int128, vector unsigned __int128);
|
||||
vector bool __int128 vec_cmpne (vector signed __int128, vector signed __int128);
|
||||
vector bool __int128 vec_cmpne (vector unsigned __int128, vector unsigned __int128);
|
||||
vector bool __int128 vec_cmpgt (vector signed __int128, vector signed __int128);
|
||||
vector bool __int128 vec_cmpgt (vector unsigned __int128, vector unsigned __int128);
|
||||
vector bool __int128 vec_cmplt (vector signed __int128, vector signed __int128);
|
||||
vector bool __int128 vec_cmplt (vector unsigned __int128, vector unsigned __int128);
|
||||
vector bool __int128 vec_cmpge (vector signed __int128, vector signed __int128);
|
||||
vector bool __int128 vec_cmpge (vector unsigned __int128, vector unsigned __int128);
|
||||
vector bool __int128 vec_cmple (vector signed __int128, vector signed __int128);
|
||||
vector bool __int128 vec_cmple (vector unsigned __int128, vector unsigned __int128);
|
||||
|
||||
int vec_all_eq (vector signed __int128, vector signed __int128);
|
||||
int vec_all_eq (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_all_ne (vector signed __int128, vector signed __int128);
|
||||
int vec_all_ne (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_all_gt (vector signed __int128, vector signed __int128);
|
||||
int vec_all_gt (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_all_lt (vector signed __int128, vector signed __int128);
|
||||
int vec_all_lt (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_all_ge (vector signed __int128, vector signed __int128);
|
||||
int vec_all_ge (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_all_le (vector signed __int128, vector signed __int128);
|
||||
int vec_all_le (vector unsigned __int128, vector unsigned __int128);
|
||||
|
||||
int vec_any_eq (vector signed __int128, vector signed __int128);
|
||||
int vec_any_eq (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_any_ne (vector signed __int128, vector signed __int128);
|
||||
int vec_any_ne (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_any_gt (vector signed __int128, vector signed __int128);
|
||||
int vec_any_gt (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_any_lt (vector signed __int128, vector signed __int128);
|
||||
int vec_any_lt (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_any_ge (vector signed __int128, vector signed __int128);
|
||||
int vec_any_ge (vector unsigned __int128, vector unsigned __int128);
|
||||
int vec_any_le (vector signed __int128, vector signed __int128);
|
||||
int vec_any_le (vector unsigned __int128, vector unsigned __int128);
|
||||
@end smallexample
|
||||
|
||||
|
||||
@node PowerPC Hardware Transactional Memory Built-in Functions
|
||||
@subsection PowerPC Hardware Transactional Memory Built-in Functions
|
||||
GCC provides two interfaces for accessing the Hardware Transactional
|
||||
|
|
|
|||
2263
gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
Normal file
2263
gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
Normal file
File diff suppressed because it is too large
Load diff
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Add table
Reference in a new issue