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x86-tune-costs.h (generic_cost, core_cost): Correct costs of x87 and SSE instructions.

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* x86-tune-costs.h (generic_cost, core_cost): Correct costs
	of x87 and SSE instructions.

From-SVN: r253911
This commit is contained in:
Jan Hubicka 2017-10-19 22:43:30 +02:00 • committed by Jan Hubicka
parent ef30ab837c
commit ef9eec0b59
2 changed files with 26 additions and 22 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2017-10-19 Jan Hubicka <hubicka@ucw.cz>
* x86-tune-costs.h (generic_cost, core_cost): Correct costs
of x87 and SSE instructions.
2017-10-19 Jan Hubicka <hubicka@ucw.cz>
* asan.c (create_cond_insert_point): Do not update edge count.

43
gcc/config/i386/x86-tune-costs.h
View file

@ -2196,8 +2196,7 @@ static stringop_algs generic_memset[2] = {
static const
struct processor_costs generic_cost = {
COSTS_N_INSNS (1), /* cost of an add instruction */
/* On all chips taken into consideration lea is 2 cycles and more. With
this cost however our current implementation of synth_mult results in
/* Setting cost to 2 makes our current implementation of synth_mult result in
use of unnecessary temporary registers causing regression on several
SPECfp benchmarks. */
COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
@ -2246,23 +2245,23 @@ struct processor_costs generic_cost = {
/* Benchmarks shows large regressions on K8 sixtrack benchmark when this
value is increased to perhaps more appropriate value of 5. */
3, /* Branch cost */
COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (8), /* cost of FMUL instruction. */
COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (3), /* cost of FMUL instruction. */
COSTS_N_INSNS (20), /* cost of FDIV instruction. */
COSTS_N_INSNS (8), /* cost of FABS instruction. */
COSTS_N_INSNS (8), /* cost of FCHS instruction. */
COSTS_N_INSNS (1), /* cost of FABS instruction. */
COSTS_N_INSNS (1), /* cost of FCHS instruction. */
COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
COSTS_N_INSNS (8), /* cost of cheap SSE instruction. */
COSTS_N_INSNS (8), /* cost of ADDSS/SD SUBSS/SD insns. */
COSTS_N_INSNS (8), /* cost of MULSS instruction. */
COSTS_N_INSNS (8), /* cost of MULSD instruction. */
COSTS_N_INSNS (8), /* cost of FMA SS instruction. */
COSTS_N_INSNS (8), /* cost of FMA SD instruction. */
COSTS_N_INSNS (20), /* cost of DIVSS instruction. */
COSTS_N_INSNS (20), /* cost of DIVSD instruction. */
COSTS_N_INSNS (40), /* cost of SQRTSS instruction. */
COSTS_N_INSNS (40), /* cost of SQRTSD instruction. */
COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
COSTS_N_INSNS (4), /* cost of MULSS instruction. */
COSTS_N_INSNS (5), /* cost of MULSD instruction. */
COSTS_N_INSNS (5), /* cost of FMA SS instruction. */
COSTS_N_INSNS (5), /* cost of FMA SD instruction. */
COSTS_N_INSNS (18), /* cost of DIVSS instruction. */
COSTS_N_INSNS (32), /* cost of DIVSD instruction. */
COSTS_N_INSNS (30), /* cost of SQRTSS instruction. */
COSTS_N_INSNS (58), /* cost of SQRTSD instruction. */
1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */
generic_memcpy,
generic_memset,
@ -2344,12 +2343,12 @@ struct processor_costs core_cost = {
6, /* number of parallel prefetches */
/* FIXME perhaps more appropriate value is 5. */
3, /* Branch cost */
COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (8), /* cost of FMUL instruction. */
COSTS_N_INSNS (20), /* cost of FDIV instruction. */
COSTS_N_INSNS (8), /* cost of FABS instruction. */
COSTS_N_INSNS (8), /* cost of FCHS instruction. */
COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (5), /* cost of FMUL instruction. */
COSTS_N_INSNS (24), /* cost of FDIV instruction. */
COSTS_N_INSNS (1), /* cost of FABS instruction. */
COSTS_N_INSNS (1), /* cost of FCHS instruction. */
COSTS_N_INSNS (24), /* cost of FSQRT instruction. */
COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */