i386.md (floatdi?f): Avoid usinf of SSE instructions if TARGET_64BIT is false.
* i386.md (floatdi?f): Avoid usinf of SSE instructions if TARGET_64BIT is false. (floatdi?f_i386_only): New insn. (floatdi?f_i386): Disable for !TARGET_64BIT. * (min?f, max?f splitters): Handle case where operands are cross-matched. * i386.h (HI_REGISTER_NAMES): Remove redundant definition (MMX_REGISTER_NAMES): Kill. (PRINT_OPERAND): Fix comment. (PRINT_REG): Likewise. * i386.c (print_reg): Kill support for 'm' CODE; simplify. (print_operand): Update comment; kill 'm'. * i386.c (x86_branch_hints): New global variable (print_operand): Support outputting of branch prediction hints. * i386.md (conditional jump patterns): Add branch prediction hints to the template. * i386.h (x86_branch_hints): Declare (TARGET_BRANCH_PREDICTION_HINTS): New macro. (PRINT_OPERAND_FUNCT_VALID_P): New. * final.c (final_forward_branch_p): New function. From-SVN: r42945
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
3b8fd08f82
commit
ef6257cdab
5 changed files with 190 additions and 72 deletions
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@ -1,3 +1,29 @@
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Wed Jun 6 14:51:05 CEST 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (floatdi?f): Avoid usinf of SSE instructions
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if TARGET_64BIT is false.
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(floatdi?f_i386_only): New insn.
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(floatdi?f_i386): Disable for !TARGET_64BIT.
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* (min?f, max?f splitters): Handle case where
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operands are cross-matched.
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* i386.h (HI_REGISTER_NAMES): Remove redundant definition
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(MMX_REGISTER_NAMES): Kill.
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(PRINT_OPERAND): Fix comment.
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(PRINT_REG): Likewise.
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* i386.c (print_reg): Kill support for 'm' CODE; simplify.
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(print_operand): Update comment; kill 'm'.
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* i386.c (x86_branch_hints): New global variable
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(print_operand): Support outputting of branch prediction hints.
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* i386.md (conditional jump patterns): Add branch prediction hints
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to the template.
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* i386.h (x86_branch_hints): Declare
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(TARGET_BRANCH_PREDICTION_HINTS): New macro.
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(PRINT_OPERAND_FUNCT_VALID_P): New.
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* final.c (final_forward_branch_p): New function.
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2001-06-06 Richard Henderson <rth@redhat.com>
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* flow.c (mark_used_reg): Clean up looping over multiple hard
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@ -290,6 +290,7 @@ const int x86_use_bit_test = m_386;
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const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON | m_K6;
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const int x86_cmove = m_PPRO | m_ATHLON | m_PENT4;
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const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON | m_PENT4;
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const int x86_branch_hints = m_PENT4;
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const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4;
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const int x86_partial_reg_stall = m_PPRO;
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const int x86_use_loop = m_K6;
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@ -3796,7 +3797,7 @@ print_reg (x, code, file)
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if (ASSEMBLER_DIALECT == 0 || USER_LABEL_PREFIX[0] == 0)
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putc ('%', file);
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if (code == 'w')
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if (code == 'w' || MMX_REG_P (x))
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code = 2;
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else if (code == 'b')
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code = 1;
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@ -3808,8 +3809,6 @@ print_reg (x, code, file)
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code = 3;
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else if (code == 'h')
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code = 0;
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else if (code == 'm' || MMX_REG_P (x))
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code = 5;
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else
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code = GET_MODE_SIZE (GET_MODE (x));
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@ -3821,7 +3820,7 @@ print_reg (x, code, file)
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abort ();
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switch (code)
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{
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case 5:
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case 0:
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error ("Extended registers have no high halves\n");
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break;
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case 1:
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@ -3844,9 +3843,6 @@ print_reg (x, code, file)
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}
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switch (code)
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{
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case 5:
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fputs (hi_reg_name[REGNO (x)], file);
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break;
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case 3:
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if (STACK_TOP_P (x))
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{
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@ -3879,6 +3875,7 @@ print_reg (x, code, file)
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L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
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C -- print opcode suffix for set/cmov insn.
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c -- like C, but print reversed condition
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F,f -- likewise, but for floating-point.
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R -- print the prefix for register names.
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z -- print the opcode suffix for the size of the current operand.
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* -- print a star (in certain assembler syntax)
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@ -3891,10 +3888,11 @@ print_reg (x, code, file)
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w -- likewise, print the HImode name of the register.
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k -- likewise, print the SImode name of the register.
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q -- likewise, print the DImode name of the register.
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h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
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y -- print "st(0)" instead of "st" as a register.
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m -- print "st(n)" as an mmx register.
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h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
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y -- print "st(0)" instead of "st" as a register.
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D -- print condition for SSE cmp instruction.
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P -- if PIC, print an @PLT suffix.
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X -- don't print any sort of PIC '@' suffix for a symbol.
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*/
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void
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@ -4017,7 +4015,6 @@ print_operand (file, x, code)
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case 'q':
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case 'h':
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case 'y':
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case 'm':
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case 'X':
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case 'P':
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break;
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@ -4085,7 +4082,39 @@ print_operand (file, x, code)
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case 'f':
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put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
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return;
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case '+':
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{
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rtx x;
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if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
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return;
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x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
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if (x)
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{
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int pred_val = INTVAL (XEXP (x, 0));
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if (pred_val < REG_BR_PROB_BASE * 45 / 100
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|| pred_val > REG_BR_PROB_BASE * 55 / 100)
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{
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int taken = pred_val > REG_BR_PROB_BASE / 2;
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int cputaken = final_forward_branch_p (current_output_insn) == 0;
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/* Emit hints only in the case default branch prediction
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heruistics would fail. */
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if (taken != cputaken)
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{
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/* We use 3e (DS) prefix for taken branches and
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2e (CS) prefix for not taken branches. */
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if (taken)
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fputs ("ds ; ", file);
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else
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fputs ("cs ; ", file);
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}
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}
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}
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return;
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}
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default:
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{
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char str[50];
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@ -202,7 +202,7 @@ extern int target_flags;
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#define CPUMASK (1 << ix86_cpu)
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extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
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extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
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extern const int x86_unroll_strlen;
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extern const int x86_branch_hints, x86_unroll_strlen;
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extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
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extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
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extern const int x86_use_cltd, x86_read_modify_write;
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@ -222,6 +222,7 @@ extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
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safe to enable all CMOVE instructions. */
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#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
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#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
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#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
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#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
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#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
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#define TARGET_MOVX (x86_movx & CPUMASK)
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@ -2755,11 +2756,6 @@ while (0)
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For float regs, the stack top is sometimes referred to as "%st(0)"
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instead of just "%st". PRINT_REG handles this with the "y" code. */
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#define HI_REGISTER_NAMES \
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{"ax","dx","cx","bx","si","di","bp","sp", \
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"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
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"flags","fpsr", "dirflag", "frame" }
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#undef HI_REGISTER_NAMES
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#define HI_REGISTER_NAMES \
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{"ax","dx","cx","bx","si","di","bp","sp", \
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@ -2798,9 +2794,6 @@ number as al, and ax.
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#define QI_HIGH_REGISTER_NAMES \
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{"ah", "dh", "ch", "bh", }
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#define MMX_REGISTER_NAMES \
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{0,0,0,0,0,0,0,0,"mm0","mm1","mm2","mm3","mm4","mm5","mm6","mm7"}
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/* How to renumber registers for dbx and gdb. */
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#define DBX_REGISTER_NUMBER(n) \
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@ -2970,33 +2963,19 @@ do { long l; \
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/* Print operand X (an rtx) in assembler syntax to file FILE.
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CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
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The CODE z takes the size of operand from the following digit, and
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outputs b,w,or l respectively.
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On the 80386, we use several such letters:
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f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
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L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
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R -- print the prefix for register names.
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z -- print the opcode suffix for the size of the current operand.
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* -- print a star (in certain assembler syntax)
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A -- print an absolute memory reference.
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P -- if PIC, print an @PLT suffix.
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X -- don't print any sort of PIC '@' suffix for a symbol.
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s -- ??? something to do with double shifts. not actually used, afaik.
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C -- print a conditional move suffix corresponding to the op code.
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c -- likewise, but reverse the condition.
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F,f -- likewise, but for floating-point. */
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Effect of various CODE letters is described in i386.c near
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print_operand function. */
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#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
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((CODE) == '*')
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((CODE) == '*' || (CODE) == '+')
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/* Print the name of a register based on its machine mode and number.
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If CODE is 'w', pretend the mode is HImode.
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If CODE is 'b', pretend the mode is QImode.
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If CODE is 'k', pretend the mode is SImode.
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If CODE is 'd', pretend the mode is DImode.
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If CODE is 'q', pretend the mode is DImode.
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If CODE is 'h', pretend the reg is the `high' byte register.
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If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
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If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
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#define PRINT_REG(X, CODE, FILE) \
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print_reg (X, CODE, FILE)
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@ -4721,7 +4721,7 @@
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"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
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"
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{
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if (TARGET_SSE2)
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if (TARGET_SSE2 && TARGET_64BIT)
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{
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rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
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emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
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@ -4746,7 +4746,7 @@
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"TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
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"
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{
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if (TARGET_SSE2)
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if (TARGET_SSE2 && TARGET_64BIT)
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{
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rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
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emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
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@ -5070,10 +5070,21 @@
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"(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
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"")
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(define_insn "*floatdisf2_i387_only"
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[(set (match_operand:SF 0 "register_operand" "=f,?f")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
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"TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
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"@
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fild%z1\\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "SF")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatdisf2_i387"
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[(set (match_operand:SF 0 "register_operand" "=f,?f,x")
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(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
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"TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
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"TARGET_80387 && TARGET_64BIT && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
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"@
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fild%z1\\t%1
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#
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@ -5135,10 +5146,21 @@
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"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
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"")
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(define_insn "*floatdidf2_i387_only"
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[(set (match_operand:DF 0 "register_operand" "=f,?f")
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
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"TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
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"@
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fild%z1\\t%1
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#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "DF")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatdidf2_i387"
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[(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
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(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
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"TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
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"TARGET_80387 && TARGET_64BIT && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
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"@
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fild%z1\\t%1
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#
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@ -5585,6 +5607,8 @@
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/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
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if (GET_CODE (operands[2]) == CONST_INT
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/* Avoid overflows. */
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&& ((INTVAL (operands[2]) & ((1 << 31) - 1)))
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&& (INTVAL (operands[2]) == 128
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|| (INTVAL (operands[2]) < 0
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&& INTVAL (operands[2]) != -128)))
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@ -5656,6 +5680,8 @@
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/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
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if (GET_CODE (operands[2]) == CONST_INT
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/* Avoid overflows. */
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&& ((INTVAL (operands[2]) & ((1 << 31) - 1)))
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&& (INTVAL (operands[2]) == 128
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|| (INTVAL (operands[2]) < 0
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&& INTVAL (operands[2]) != -128)))
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@ -5705,6 +5731,8 @@
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/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
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if (GET_CODE (operands[2]) == CONST_INT
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/* Avoid overflows. */
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&& ((INTVAL (operands[2]) & ((1 << 31) - 1)))
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&& (INTVAL (operands[2]) == 128
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|| (INTVAL (operands[2]) < 0
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&& INTVAL (operands[2]) != -128)))
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|
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@ -5755,7 +5783,9 @@
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
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if ((INTVAL (operands[2]) == -128
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|| (INTVAL (operands[2]) > 0
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&& INTVAL (operands[2]) != 128)))
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&& INTVAL (operands[2]) != 128))
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/* Avoid overflows. */
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&& ((INTVAL (operands[2]) & ((1 << 31) - 1))))
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return \"sub{q}\\t{%2, %0|%0, %2}\";
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operands[2] = GEN_INT (-INTVAL (operands[2]));
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return \"add{q}\\t{%2, %0|%0, %2}\";
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@ -5800,6 +5830,8 @@
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/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
|
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if (GET_CODE (operands[2]) == CONST_INT
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/* Avoid overflows. */
|
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&& ((INTVAL (operands[2]) & ((1 << 31) - 1)))
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&& (INTVAL (operands[2]) == 128
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|| (INTVAL (operands[2]) < 0
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&& INTVAL (operands[2]) != -128)))
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|
|
@ -12750,7 +12782,7 @@
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|||
(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"j%C1\\t%l0"
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"%+j%C1\\t%l0"
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[(set_attr "type" "ibr")
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(set (attr "prefix_0f")
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(if_then_else (and (ge (minus (match_dup 0) (pc))
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|
|
@ -12767,7 +12799,7 @@
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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""
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||||
"j%c1\\t%l0"
|
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"%+j%c1\\t%l0"
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[(set_attr "type" "ibr")
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||||
(set (attr "prefix_0f")
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(if_then_else (and (ge (minus (match_dup 0) (pc))
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|
|
@ -13110,9 +13142,9 @@
|
|||
if (which_alternative != 0)
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||||
return \"#\";
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||||
if (get_attr_length (insn) == 2)
|
||||
return \"loop\\t%l0\";
|
||||
return \"%+loop\\t%l0\";
|
||||
else
|
||||
return \"dec{l}\\t%1\;jne\\t%l0\";
|
||||
return \"dec{l}\\t%1\;%+jne\\t%l0\";
|
||||
}"
|
||||
[(set_attr "ppro_uops" "many")
|
||||
(set (attr "type")
|
||||
|
|
@ -15806,10 +15838,14 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "")
|
||||
(if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
|
||||
(match_operand:SF 2 "nonimmediate_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:DF 3 "register_operand" "")
|
||||
(match_operand:DF 4 "nonimmediate_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"SSE_REG_P (operands[0]) && reload_completed"
|
||||
"SSE_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (match_dup 0)
|
||||
(if_then_else:SF (lt (match_dup 1)
|
||||
(match_dup 2))
|
||||
|
|
@ -15817,14 +15853,19 @@
|
|||
(match_dup 2)))])
|
||||
|
||||
;; We can't represent the LT test directly. Do this by swapping the operands.
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SF 0 "register_operand" "")
|
||||
(if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
|
||||
(match_operand:SF 2 "register_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:DF 3 "register_operand" "")
|
||||
(match_operand:DF 4 "register_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"FP_REG_P (operands[0]) && reload_completed"
|
||||
"FP_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (reg:CCFP 17)
|
||||
(compare:CCFP (match_dup 2)
|
||||
(match_dup 1)))
|
||||
|
|
@ -15879,10 +15920,14 @@
|
|||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
|
||||
(match_operand:DF 2 "nonimmediate_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:DF 3 "register_operand" "")
|
||||
(match_operand:DF 4 "nonimmediate_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"SSE_REG_P (operands[0]) && reload_completed"
|
||||
"SSE_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (match_dup 0)
|
||||
(if_then_else:DF (lt (match_dup 1)
|
||||
(match_dup 2))
|
||||
|
|
@ -15894,10 +15939,14 @@
|
|||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
|
||||
(match_operand:DF 2 "register_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:DF 3 "register_operand" "")
|
||||
(match_operand:DF 4 "register_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"FP_REG_P (operands[0]) && reload_completed"
|
||||
"FP_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (reg:CCFP 17)
|
||||
(compare:CCFP (match_dup 2)
|
||||
(match_dup 2)))
|
||||
|
|
@ -15952,10 +16001,14 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "")
|
||||
(if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
|
||||
(match_operand:SF 2 "nonimmediate_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:SF 3 "register_operand" "")
|
||||
(match_operand:SF 4 "nonimmediate_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"SSE_REG_P (operands[0]) && reload_completed"
|
||||
"SSE_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (match_dup 0)
|
||||
(if_then_else:SF (gt (match_dup 1)
|
||||
(match_dup 2))
|
||||
|
|
@ -15966,10 +16019,14 @@
|
|||
[(set (match_operand:SF 0 "register_operand" "")
|
||||
(if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
|
||||
(match_operand:SF 2 "register_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:SF 3 "register_operand" "")
|
||||
(match_operand:SF 4 "register_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"FP_REG_P (operands[0]) && reload_completed"
|
||||
"FP_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (reg:CCFP 17)
|
||||
(compare:CCFP (match_dup 1)
|
||||
(match_dup 2)))
|
||||
|
|
@ -16024,10 +16081,14 @@
|
|||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
|
||||
(match_operand:DF 2 "nonimmediate_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:DF 3 "register_operand" "")
|
||||
(match_operand:DF 4 "nonimmediate_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"SSE_REG_P (operands[0]) && reload_completed"
|
||||
"SSE_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (match_dup 0)
|
||||
(if_then_else:DF (gt (match_dup 1)
|
||||
(match_dup 2))
|
||||
|
|
@ -16038,10 +16099,14 @@
|
|||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
|
||||
(match_operand:DF 2 "register_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_operand:DF 3 "register_operand" "")
|
||||
(match_operand:DF 4 "register_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"FP_REG_P (operands[0]) && reload_completed"
|
||||
"FP_REG_P (operands[0]) && reload_completed
|
||||
&& ((operands_match_p (operands[1], operands[3])
|
||||
&& operands_match_p (operands[2], operands[4]))
|
||||
|| (operands_match_p (operands[1], operands[4])
|
||||
&& operands_match_p (operands[2], operands[3])))"
|
||||
[(set (reg:CCFP 17)
|
||||
(compare:CCFP (match_dup 1)
|
||||
(match_dup 2)))
|
||||
|
|
|
|||
19
gcc/final.c
19
gcc/final.c
|
|
@ -4086,6 +4086,25 @@ leaf_function_p ()
|
|||
return 1;
|
||||
}
|
||||
|
||||
/* Return 1 if branch is an forward branch.
|
||||
Uses insn_shuid array, so it works only in the final pass. May be used by
|
||||
output templates to customary add branch prediction hints.
|
||||
*/
|
||||
int
|
||||
final_forward_branch_p (insn)
|
||||
rtx insn;
|
||||
{
|
||||
int insn_id, label_id;
|
||||
if (!uid_shuid)
|
||||
abort ();
|
||||
insn_id = INSN_SHUID (insn);
|
||||
label_id = INSN_SHUID (JUMP_LABEL (insn));
|
||||
/* We've hit some insns that does not have id information available. */
|
||||
if (!insn_id || !label_id)
|
||||
abort ();
|
||||
return insn_id < label_id;
|
||||
}
|
||||
|
||||
/* On some machines, a function with no call insns
|
||||
can run faster if it doesn't create its own register window.
|
||||
When output, the leaf function should use only the "output"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue