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arm.c (thumb2_reorg): New function.

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* config/arm/arm.c (thumb2_reorg): New function.
	(arm_reorg): Call it.
	* config/arm/thumb2.md (define_peephole2 for flag clobbering
	arithmetic operations): Delete.

From-SVN: r160458
This commit is contained in:
Bernd Schmidt 2010-06-09 09:46:55 +00:00 • committed by Bernd Schmidt
parent dbd34b899f
commit eef5973df4
3 changed files with 65 additions and 23 deletions
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7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2010-06-09 Bernd Schmidt <bernds@codesourcery.com>
* config/arm/arm.c (thumb2_reorg): New function.
(arm_reorg): Call it.
* config/arm/thumb2.md (define_peephole2 for flag clobbering
arithmetic operations): Delete.
2010-06-09 Edmar Wienskoski <edmar@freescale.com>
PR target/44067

58
gcc/config/arm/arm.c
View file

@ -11421,6 +11421,61 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
return result;
}
/* Convert instructions to their cc-clobbering variant if possible, since
that allows us to use smaller encodings. */
static void
thumb2_reorg (void)
{
basic_block bb;
regset_head live;
INIT_REG_SET (&live);
/* We are freeing block_for_insn in the toplev to keep compatibility
with old MDEP_REORGS that are not CFG based. Recompute it now. */
compute_bb_for_insn ();
df_analyze ();
FOR_EACH_BB (bb)
{
rtx insn;
COPY_REG_SET (&live, DF_LR_OUT (bb));
df_simulate_initialize_backwards (bb, &live);
FOR_BB_INSNS_REVERSE (bb, insn)
{
if (NONJUMP_INSN_P (insn)
&& !REGNO_REG_SET_P (&live, CC_REGNUM))
{
rtx pat = PATTERN (insn);
if (GET_CODE (pat) == SET
&& low_register_operand (XEXP (pat, 0), SImode)
&& thumb_16bit_operator (XEXP (pat, 1), SImode)
&& low_register_operand (XEXP (XEXP (pat, 1), 0), SImode)
&& low_register_operand (XEXP (XEXP (pat, 1), 1), SImode))
{
rtx dst = XEXP (pat, 0);
rtx src = XEXP (pat, 1);
rtx op0 = XEXP (src, 0);
rtx op1 = XEXP (src, 1);
if (rtx_equal_p (dst, op0)
|| GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
{
rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
rtx vec = gen_rtvec (2, pat, clobber);
PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
INSN_CODE (insn) = -1;
}
}
}
if (NONDEBUG_INSN_P (insn))
df_simulate_one_insn_backwards (bb, insn, &live);
}
}
CLEAR_REG_SET (&live);
}
/* Gcc puts the pool in the wrong place for ARM, since we can only
load addresses a limited distance around the pc. We do some
special munging to move the constant pool values to the correct
@ -11432,6 +11487,9 @@ arm_reorg (void)
HOST_WIDE_INT address = 0;
Mfix * fix;
if (TARGET_THUMB2)
thumb2_reorg ();
minipool_fix_head = minipool_fix_tail = NULL;
/* The first insn must always be a note, or the code below won't

23
gcc/config/arm/thumb2.md
View file

@ -1082,29 +1082,6 @@
}"
)
;; Peepholes and insns for 16-bit flag clobbering instructions.
;; The conditional forms of these instructions do not clobber CC.
;; However by the time peepholes are run it is probably too late to do
;; anything useful with this information.
(define_peephole2
[(set (match_operand:SI 0 "low_register_operand" "")
(match_operator:SI 3 "thumb_16bit_operator"
[(match_operand:SI 1 "low_register_operand" "")
(match_operand:SI 2 "low_register_operand" "")]))]
"TARGET_THUMB2
&& (rtx_equal_p(operands[0], operands[1])
|| GET_CODE(operands[3]) == PLUS
|| GET_CODE(operands[3]) == MINUS)
&& peep2_regno_dead_p(0, CC_REGNUM)"
[(parallel
[(set (match_dup 0)
(match_op_dup 3
[(match_dup 1)
(match_dup 2)]))
(clobber (reg:CC CC_REGNUM))])]
""
)
(define_insn "*thumb2_alusi3_short"
[(set (match_operand:SI 0 "s_register_operand" "=l")
(match_operator:SI 3 "thumb_16bit_operator"