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RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit

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Previously,  I add TARGET_64BIT condtion to block VLS modes with size = 64bit in RV32 system
E.g. V8QI

Since I realized such modes may cause inferior codegen for some situations in RV32 system.

However, this is really quite ugly and it cause ICE for some cases in RV32:

FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (internal compiler error: in require, at machmode.h:313)
3937FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (test for excess errors)

For inferior codegen in RV32 system, we should try another reasonable approach to fix it.

Remove those TARGET_64BIT and fix ICE.

gcc/ChangeLog:

	* config/riscv/riscv-vector-switch.def (VLS_ENTRY): Remove TARGET_64BIT

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64x-1.c: Ditto.
This commit is contained in:
Juzhe-Zhong 2023-09-06 20:18:14 +08:00 • committed by Pan Li
parent f2d7a4001a
commit ee21f79f72
17 changed files with 20 additions and 20 deletions
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8
gcc/config/riscv/riscv-vector-switch.def
View file

@ -309,7 +309,7 @@ VLS_ENTRY (V4096BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V2QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V4QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V8QI, TARGET_VECTOR_VLS && TARGET_64BIT)
VLS_ENTRY (V8QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V16QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V32QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V64QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64)
@ -321,7 +321,7 @@ VLS_ENTRY (V2048QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048)
VLS_ENTRY (V4096QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V2HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V4HI, TARGET_VECTOR_VLS && TARGET_64BIT)
VLS_ENTRY (V4HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V8HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V16HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V32HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64)
@ -332,7 +332,7 @@ VLS_ENTRY (V512HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024)
VLS_ENTRY (V1024HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048)
VLS_ENTRY (V2048HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V2SI, TARGET_VECTOR_VLS && TARGET_64BIT)
VLS_ENTRY (V2SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V4SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V8SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V16SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64)
@ -342,7 +342,7 @@ VLS_ENTRY (V128SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512)
VLS_ENTRY (V256SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024)
VLS_ENTRY (V512SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048)
VLS_ENTRY (V1024SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_64BIT)
VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64)
VLS_ENTRY (V2DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64)
VLS_ENTRY (V4DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64)
VLS_ENTRY (V8DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64)

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
View file

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
View file

@ -3,4 +3,4 @@
#include "template-1.h"
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */