RISC-V: Add vand.vx C++ API test.
gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C: New test.
This commit is contained in:
Ju-Zhe Zhong
Kito Cheng
parent
e0e32c3397
commit
edfc440250
30 changed files with 10422 additions and 0 deletions
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C
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289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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#include "riscv_vector.h"
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vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
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{
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return __riscv_vand_mu(mask,merge,op1,op2,vl);
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}
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
572
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C
Normal file
572
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C
Normal file
|
|
@ -0,0 +1,572 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
572
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C
Normal file
572
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C
Normal file
|
|
@ -0,0 +1,572 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
572
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C
Normal file
572
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C
Normal file
|
|
@ -0,0 +1,572 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
578
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C
Normal file
578
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
578
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C
Normal file
578
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
578
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C
Normal file
578
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C
Normal file
289
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C
Normal file
292
gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vand_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
|
||||
Loading…
Add table
Reference in a new issue