procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

sse.md (sse3_mwait): Swap the operand constriants.

Browse source 
2015-06-05  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>

        * config/i386/sse.md (sse3_mwait): Swap the operand constriants.

From-SVN: r224146
This commit is contained in:
Venkataramanan Kumar 2015-06-05 06:38:32 +00:00 • committed by Venkataramanan Kumar
parent 14ae1d88b3
commit edf1fd6def
2 changed files with 9 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
gcc/ChangeLog
View file

@ -1,3 +1,7 @@
2015-06-05 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
* config/i386/sse.md (sse3_mwait): Swap the operand constriants.
2015-06-04 DJ Delorie <dj@redhat.com>
* config/msp430/msp430.md (movsi_s): New. Special case for

8
gcc/config/i386/sse.md
View file

@ -13218,10 +13218,12 @@
(set_attr "atom_sse_attr" "fence")
(set_attr "memory" "unknown")])
;; As per AMD and Intel ISA manuals, the first operand is extensions
;; and it goes to %ecx. The second operand received is hints and it goes
;; to %eax.
(define_insn "sse3_mwait"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
(match_operand:SI 1 "register_operand" "c")]
[(unspec_volatile [(match_operand:SI 0 "register_operand" "c")
(match_operand:SI 1 "register_operand" "a")]
UNSPECV_MWAIT)]
"TARGET_SSE3"
;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.