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Update prefixed attribute for Power10.

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This patch creates a new attribute, "maybe_prefixed", which is used to mark
those instructions that may have a prefixed form. The existing "prefixed"
attribute is now used to mark all instructions that are prefixed form.

2021-03-31  Pat Haugen  <pthaugen@linux.ibm.com>

gcc/
	PR target/99133
	* config/rs6000/altivec.md (xxspltiw_v4si, xxspltiw_v4sf_inst,
	xxspltidp_v2df_inst, xxsplti32dx_v4si_inst, xxsplti32dx_v4sf_inst,
	xxblend_<mode>, xxpermx_inst, xxeval): Mark prefixed.
	* config/rs6000/mma.md (mma_<vvi4i4i8>, mma_<avvi4i4i8>,
	mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>,
	mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>):
	Likewise.
	* config/rs6000/rs6000.c (rs6000_final_prescan_insn): Adjust test.
	* config/rs6000/rs6000.md (define_attr "maybe_prefixed"): New.
	(define_attr "prefixed"): Update initializer.
This commit is contained in:
Pat Haugen 2021-03-31 14:37:24 -05:00
parent 4b33c5aaab
commit ea9a39e63e
4 changed files with 52 additions and 25 deletions
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24
gcc/config/rs6000/altivec.md
View file

@ -826,7 +826,8 @@
UNSPEC_XXSPLTIW))]
"TARGET_POWER10"
"xxspltiw %x0,%1"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "xxspltiw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=wa")
@ -845,7 +846,8 @@
UNSPEC_XXSPLTIW))]
"TARGET_POWER10"
"xxspltiw %x0,%1"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "xxspltidp_v2df"
[(set (match_operand:V2DF 0 "register_operand" )
@ -864,7 +866,8 @@
UNSPEC_XXSPLTID))]
"TARGET_POWER10"
"xxspltidp %x0,%1"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
@ -893,7 +896,8 @@
UNSPEC_XXSPLTI32DX))]
"TARGET_POWER10"
"xxsplti32dx %x0,%2,%3"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "xxsplti32dx_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=wa")
@ -921,7 +925,8 @@
UNSPEC_XXSPLTI32DX))]
"TARGET_POWER10"
"xxsplti32dx %x0,%2,%3"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
@ -931,7 +936,8 @@
UNSPEC_XXBLEND))]
"TARGET_POWER10"
"xxblendv<VM3_char> %x0,%x1,%x2,%x3"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "xxpermx"
[(set (match_operand:V2DI 0 "register_operand" "+wa")
@ -975,7 +981,8 @@
UNSPEC_XXPERMX))]
"TARGET_POWER10"
"xxpermx %x0,%x1,%x2,%x3,%4"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
@ -3623,7 +3630,8 @@
UNSPEC_XXEVAL))]
"TARGET_POWER10"
"xxeval %0,%1,%2,%3,%4"
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
(define_expand "vec_unpacku_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")

30
gcc/config/rs6000/mma.md
View file

@ -540,7 +540,8 @@
MMA_VVI4I4I8))]
"TARGET_MMA"
"<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i8>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -553,7 +554,8 @@
MMA_AVVI4I4I8))]
"TARGET_MMA"
"<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4i2>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -565,7 +567,8 @@
MMA_VVI4I4I2))]
"TARGET_MMA"
"<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i2>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -578,7 +581,8 @@
MMA_AVVI4I4I2))]
"TARGET_MMA"
"<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -589,7 +593,8 @@
MMA_VVI4I4))]
"TARGET_MMA"
"<vvi4i4> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -601,7 +606,8 @@
MMA_AVVI4I4))]
"TARGET_MMA"
"<avvi4i4> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<pvi4i2>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -612,7 +618,8 @@
MMA_PVI4I2))]
"TARGET_MMA"
"<pvi4i2> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<apvi4i2>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -624,7 +631,8 @@
MMA_APVI4I2))]
"TARGET_MMA"
"<apvi4i2> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<vvi4i4i4>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -636,7 +644,8 @@
MMA_VVI4I4I4))]
"TARGET_MMA"
"<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
(define_insn "mma_<avvi4i4i4>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@ -649,4 +658,5 @@
MMA_AVVI4I4I4))]
"TARGET_MMA"
"<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")])
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])

4
gcc/config/rs6000/rs6000.c
View file

@ -26396,7 +26396,9 @@ static bool prepend_p_to_next_insn;
void
rs6000_final_prescan_insn (rtx_insn *insn, rtx [], int)
{
prepend_p_to_next_insn = (get_attr_prefixed (insn) != PREFIXED_NO);
prepend_p_to_next_insn = (get_attr_maybe_prefixed (insn)
== MAYBE_PREFIXED_YES
&& get_attr_prefixed (insn) == PREFIXED_YES);
return;
}

19
gcc/config/rs6000/rs6000.md
View file

@ -264,15 +264,22 @@
(define_attr "cannot_copy" "no,yes" (const_string "no"))
;; Whether an insn is a prefixed insn, and an initial 'p' should be printed
;; before the instruction. A prefixed instruction has a prefix instruction
;; word that extends the immediate value of the instructions from 12-16 bits to
;; 34 bits. The macro ASM_OUTPUT_OPCODE emits a leading 'p' for prefixed
;; insns. The default "length" attribute will also be adjusted by default to
;; Whether this insn has a prefixed form and a non-prefixed form.
(define_attr "maybe_prefixed" "no,yes"
(if_then_else (eq_attr "type" "load,fpload,vecload,store,fpstore,vecstore,
integer,add")
(const_string "yes")
(const_string "no")))
;; Whether an insn is a prefixed insn. A prefixed instruction has a prefix
;; instruction word that conveys additional information such as a larger
;; immediate, additional operands, etc., in addition to the normal instruction
;; word. The default "length" attribute will also be adjusted by default to
;; be 12 bytes.
(define_attr "prefixed" "no,yes"
(cond [(ior (match_test "!TARGET_PREFIXED")
(match_test "!NONJUMP_INSN_P (insn)"))
(match_test "!NONJUMP_INSN_P (insn)")
(eq_attr "maybe_prefixed" "no"))
(const_string "no")
(eq_attr "type" "load,fpload,vecload")