i386: Optimize strict_low_part QImode insn with high input registers
Following testcase:
struct S1
{
unsigned char val;
unsigned char pad1;
unsigned short pad2;
};
struct S2
{
unsigned char pad1;
unsigned char val;
unsigned short pad2;
};
struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
{
a.val = b.val + c.val;
return a;
}
compiles with -O2 to:
movl %edi, %eax
movzbl %dh, %edx
movl %esi, %ecx
movb %dl, %al
addb %ch, %al
The insert to %al can go directly from %dh:
movl %edi, %eax
movl %esi, %ecx
movb %dh, %al
addb %ch, %al
Patch introduces strict_low_part QImode insn patterns with both of
their input arguments extracted from high register. This invalid
insn is split after reload to a lowpart insert from the high register
and <insn>qi_ext<mode>_1_slp instruction.
PR target/78904
gcc/ChangeLog:
* config/i386/i386.md (*movstrictqi_ext<mode>_1): New insn pattern.
(*addqi_ext<mode>_2_slp): New define_insn_and_split pattern.
(*subqi_ext<mode>_2_slp): Ditto.
(*<any_logic:code>qi_ext<mode>_2_slp): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr78904-8.c: New test.
* gcc.target/i386/pr78904-8a.c: New test.
* gcc.target/i386/pr78904-8b.c: New test.
* gcc.target/i386/pr78904-9.c: New test.
* gcc.target/i386/pr78904-9a.c: New test.
* gcc.target/i386/pr78904-9b.c: New test.
This commit is contained in:
Uros Bizjak
parent
01bc30b222
commit
e8676f9ded
7 changed files with 376 additions and 0 deletions
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@ -3335,6 +3335,19 @@
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(set_attr "mode" "<MODE>")
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(set_attr "length_immediate" "0")])
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(define_insn "*movstrictqi_ext<mode>_1"
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[(set (strict_low_part
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(match_operand:QI 0 "register_operand" "+Q"))
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(subreg:QI
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(match_operator:SWI248 2 "extract_operator"
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[(match_operand 1 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"mov{b}\t{%h1, %0|%0, %h1}"
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[(set_attr "type" "imov")
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(set_attr "mode" "QI")])
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(define_expand "extv<mode>"
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[(set (match_operand:SWI24 0 "register_operand")
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(sign_extract:SWI24 (match_operand:SWI24 1 "register_operand")
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@ -6645,6 +6658,39 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn_and_split "*addqi_ext<mode>_2_slp"
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[(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q"))
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(plus:QI
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(subreg:QI
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(match_operator:SWI248 3 "extract_operator"
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[(match_operand 1 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0)
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(subreg:QI
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(match_operator:SWI248 4 "extract_operator"
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[(match_operand 2 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"#"
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"&& reload_completed"
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[(set (strict_low_part (match_dup 0))
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(subreg:QI
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(match_op_dup 4
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[(match_dup 2) (const_int 8) (const_int 8)]) 0))
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(parallel
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[(set (strict_low_part (match_dup 0))
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(plus:QI
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(subreg:QI
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(match_op_dup 3
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[(match_dup 1) (const_int 8) (const_int 8)]) 0)
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(match_dup 0)))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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;; Split non destructive adds if we cannot use lea.
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(define_split
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[(set (match_operand:SWI48 0 "register_operand")
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@ -7688,6 +7734,39 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn_and_split "*subqi_ext<mode>_2_slp"
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[(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q"))
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(minus:QI
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(subreg:QI
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(match_operator:SWI248 3 "extract_operator"
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[(match_operand 1 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0)
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(subreg:QI
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(match_operator:SWI248 4 "extract_operator"
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[(match_operand 2 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"#"
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"&& reload_completed"
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[(set (strict_low_part (match_dup 0))
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(subreg:QI
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(match_op_dup 3
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[(match_dup 1) (const_int 8) (const_int 8)]) 0))
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(parallel
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[(set (strict_low_part (match_dup 0))
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(minus:QI
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(match_dup 0)
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(subreg:QI
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(match_op_dup 4
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[(match_dup 2) (const_int 8) (const_int 8)]) 0)))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn "*sub<mode>_2"
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[(set (reg FLAGS_REG)
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(compare
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@ -11513,6 +11592,39 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn_and_split "*<code>qi_ext<mode>_2_slp"
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[(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q"))
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(any_logic:QI
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(subreg:QI
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(match_operator:SWI248 3 "extract_operator"
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[(match_operand 1 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0)
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(subreg:QI
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(match_operator:SWI248 4 "extract_operator"
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[(match_operand 2 "int248_register_operand" "Q")
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(const_int 8)
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(const_int 8)]) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"#"
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"&& reload_completed"
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[(set (strict_low_part (match_dup 0))
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(subreg:QI
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(match_op_dup 4
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[(match_dup 2) (const_int 8) (const_int 8)]) 0))
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(parallel
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[(set (strict_low_part (match_dup 0))
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(any_logic:QI
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(subreg:QI
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(match_op_dup 3
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[(match_dup 1) (const_int 8) (const_int 8)]) 0)
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(match_dup 0)))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_split
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[(set (match_operand:SWI248 0 "register_operand")
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(and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
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25
gcc/testsuite/gcc.target/i386/pr78904-8.c
Normal file
25
gcc/testsuite/gcc.target/i386/pr78904-8.c
Normal file
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@ -0,0 +1,25 @@
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/* PR target/78904 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char val;
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unsigned char pad1;
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unsigned short pad2;
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};
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struct S2
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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struct S1 test (struct S1 a, struct S2 b)
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{
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a.val = b.val;
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return a;
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}
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23
gcc/testsuite/gcc.target/i386/pr78904-8a.c
Normal file
23
gcc/testsuite/gcc.target/i386/pr78904-8a.c
Normal file
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@ -0,0 +1,23 @@
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/* PR target/78904 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char val;
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unsigned char pad1;
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};
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struct S2
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{
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unsigned char pad1;
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unsigned char val;
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};
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struct S1 test (struct S1 a, struct S2 b)
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{
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a.val = b.val;
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return a;
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}
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27
gcc/testsuite/gcc.target/i386/pr78904-8b.c
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27
gcc/testsuite/gcc.target/i386/pr78904-8b.c
Normal file
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@ -0,0 +1,27 @@
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/* PR target/78904 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char val;
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unsigned char pad1;
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unsigned short pad2;
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unsigned int pad3;
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};
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struct S2
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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unsigned int pad3;
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};
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struct S1 test (struct S1 a, struct S2 b)
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{
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a.val = b.val;
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return a;
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}
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63
gcc/testsuite/gcc.target/i386/pr78904-9.c
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63
gcc/testsuite/gcc.target/i386/pr78904-9.c
Normal file
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@ -0,0 +1,63 @@
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/* PR target/78904 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char val;
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unsigned char pad1;
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unsigned short pad2;
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};
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struct S2
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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struct S1 test_and (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val & c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]andb" } } */
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struct S1 test_or (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val | c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]orb" } } */
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struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val ^ c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
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struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val + c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]addb" } } */
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struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val - c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]subb" } } */
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61
gcc/testsuite/gcc.target/i386/pr78904-9a.c
Normal file
61
gcc/testsuite/gcc.target/i386/pr78904-9a.c
Normal file
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@ -0,0 +1,61 @@
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/* PR target/78904 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char val;
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unsigned char pad1;
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};
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struct S2
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{
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unsigned char pad1;
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unsigned char val;
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};
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struct S1 test_and (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val & c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]andb" } } */
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struct S1 test_or (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val | c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]orb" } } */
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struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val ^ c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
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struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val + c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]addb" } } */
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struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val - c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]subb" } } */
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65
gcc/testsuite/gcc.target/i386/pr78904-9b.c
Normal file
65
gcc/testsuite/gcc.target/i386/pr78904-9b.c
Normal file
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@ -0,0 +1,65 @@
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/* PR target/78904 */
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char val;
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unsigned char pad1;
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unsigned short pad2;
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unsigned int pad3;
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};
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struct S2
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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unsigned int pad3;
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};
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struct S1 test_and (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val & c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]andb" } } */
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struct S1 test_or (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val | c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]orb" } } */
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struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val ^ c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
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struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val + c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]addb" } } */
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struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c)
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{
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a.val = b.val - c.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]subb" } } */
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