s390-protos.h (s390_alc_comparison): Add prototype.
* config/s390/s390-protos.h (s390_alc_comparison): Add prototype.
(s390_slb_comparison): Likewise.
* config/s390/s390.c (s390_alc_comparison, s390_slb_comparison):
New functions.
* config/s390/s390.h (PREDICATE_CODES): Add s390_alc_comparison
and s390_slb_comparison.
* config/s390/s390.md ("*adddi3_31", "*subdi3_31"): Do not use on
zSeries machines.
("*adddi3_31z", "*subdi3_31z"): New insns.
("*adddi3_alc_cc", "*adddi3_alc", "*subdi3_slb_cc", "*subdi3_slb",
"*addsi3_alc_cc", "*addsi3_alc", "*subsi3_slb_cc", "*subsi3_slb"):
New insns.
From-SVN: r72505
This commit is contained in:
Ulrich Weigand
Ulrich Weigand
parent
7903cebc8d
commit
e69166de8e
5 changed files with 277 additions and 3 deletions
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@ -1,3 +1,18 @@
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2003-10-14 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390-protos.h (s390_alc_comparison): Add prototype.
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(s390_slb_comparison): Likewise.
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* config/s390/s390.c (s390_alc_comparison, s390_slb_comparison):
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New functions.
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* config/s390/s390.h (PREDICATE_CODES): Add s390_alc_comparison
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and s390_slb_comparison.
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* config/s390/s390.md ("*adddi3_31", "*subdi3_31"): Do not use on
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zSeries machines.
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("*adddi3_31z", "*subdi3_31z"): New insns.
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("*adddi3_alc_cc", "*adddi3_alc", "*subdi3_slb_cc", "*subdi3_slb",
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"*addsi3_alc_cc", "*addsi3_alc", "*subsi3_slb_cc", "*subsi3_slb"):
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New insns.
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2003-10-14 Nathanael Nerode <neroden@gcc.gnu.org>
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* configure.in: Clean up some feedback echoes.
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@ -49,6 +49,8 @@ extern int tls_symbolic_operand (rtx);
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extern int s390_match_ccmode (rtx, enum machine_mode);
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extern enum machine_mode s390_tm_ccmode (rtx, rtx, int);
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extern enum machine_mode s390_select_ccmode (enum rtx_code, rtx, rtx);
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extern int s390_alc_comparison (rtx op, enum machine_mode mode);
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extern int s390_slb_comparison (rtx op, enum machine_mode mode);
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extern int symbolic_reference_mentioned_p (rtx);
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extern int tls_symbolic_reference_mentioned_p (rtx);
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extern rtx s390_tls_get_offset (void);
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@ -447,6 +447,90 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
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}
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}
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/* Return nonzero if OP is a valid comparison operator
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for an ALC condition in mode MODE. */
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int
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s390_alc_comparison (rtx op, enum machine_mode mode)
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{
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if (mode != VOIDmode && mode != GET_MODE (op))
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return 0;
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if (GET_RTX_CLASS (GET_CODE (op)) != '<')
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return 0;
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if (GET_CODE (XEXP (op, 0)) != REG
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|| REGNO (XEXP (op, 0)) != CC_REGNUM
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|| XEXP (op, 1) != const0_rtx)
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return 0;
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switch (GET_MODE (XEXP (op, 0)))
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{
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case CCL1mode:
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return GET_CODE (op) == LTU;
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case CCL2mode:
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return GET_CODE (op) == LEU;
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case CCUmode:
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return GET_CODE (op) == GTU;
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case CCURmode:
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return GET_CODE (op) == LTU;
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case CCSmode:
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return GET_CODE (op) == UNGT;
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case CCSRmode:
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return GET_CODE (op) == UNLT;
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default:
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return 0;
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}
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}
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/* Return nonzero if OP is a valid comparison operator
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for an SLB condition in mode MODE. */
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int
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s390_slb_comparison (rtx op, enum machine_mode mode)
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{
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if (mode != VOIDmode && mode != GET_MODE (op))
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return 0;
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if (GET_RTX_CLASS (GET_CODE (op)) != '<')
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return 0;
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if (GET_CODE (XEXP (op, 0)) != REG
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|| REGNO (XEXP (op, 0)) != CC_REGNUM
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|| XEXP (op, 1) != const0_rtx)
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return 0;
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switch (GET_MODE (XEXP (op, 0)))
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{
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case CCL1mode:
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return GET_CODE (op) == GEU;
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case CCL2mode:
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return GET_CODE (op) == GTU;
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case CCUmode:
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return GET_CODE (op) == LEU;
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case CCURmode:
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return GET_CODE (op) == GEU;
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case CCSmode:
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return GET_CODE (op) == LE;
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case CCSRmode:
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return GET_CODE (op) == GE;
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default:
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return 0;
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}
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}
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/* Return branch condition mask to implement a branch
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specified by CODE. */
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@ -1030,7 +1030,9 @@ do { \
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{"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
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{"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
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CONST_INT, CONST_DOUBLE }}, \
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{"s390_plus_operand", { PLUS }},
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{"s390_plus_operand", { PLUS }}, \
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{"s390_alc_comparison", { LTU, GTU, LEU, GEU }}, \
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{"s390_slb_comparison", { LTU, GTU, LEU, GEU }},
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/* Specify the machine mode that this machine uses for the index in the
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tablejump instruction. */
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@ -3254,12 +3254,37 @@
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ag\t%0,%2"
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[(set_attr "op_type" "RRE,RI,RXY")])
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(define_insn_and_split "*adddi3_31z"
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[(set (match_operand:DI 0 "register_operand" "=&d")
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(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC 33))]
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"!TARGET_64BIT && TARGET_CPU_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (reg:CCL1 33)
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(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
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(match_dup 7)))
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(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
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(parallel
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[(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
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(ltu:SI (reg:CCL1 33) (const_int 0))))
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(clobber (reg:CC 33))])]
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"operands[3] = operand_subword (operands[0], 0, 0, DImode);
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operands[4] = operand_subword (operands[1], 0, 0, DImode);
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operands[5] = operand_subword (operands[2], 0, 0, DImode);
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operands[6] = operand_subword (operands[0], 1, 0, DImode);
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operands[7] = operand_subword (operands[1], 1, 0, DImode);
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operands[8] = operand_subword (operands[2], 1, 0, DImode);"
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[(set_attr "op_type" "NN")])
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(define_insn_and_split "*adddi3_31"
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[(set (match_operand:DI 0 "register_operand" "=&d")
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(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC 33))]
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"!TARGET_64BIT"
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"!TARGET_CPU_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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@ -3804,12 +3829,37 @@
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sg\t%0,%2"
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[(set_attr "op_type" "RRE,RRE")])
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(define_insn_and_split "*subdi3_31z"
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[(set (match_operand:DI 0 "register_operand" "=&d")
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(minus:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC 33))]
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"!TARGET_64BIT && TARGET_CPU_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (reg:CCL2 33)
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(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
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(match_dup 7)))
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(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
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(parallel
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[(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
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(gtu:SI (reg:CCL2 33) (const_int 0))))
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(clobber (reg:CC 33))])]
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"operands[3] = operand_subword (operands[0], 0, 0, DImode);
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operands[4] = operand_subword (operands[1], 0, 0, DImode);
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operands[5] = operand_subword (operands[2], 0, 0, DImode);
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operands[6] = operand_subword (operands[0], 1, 0, DImode);
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operands[7] = operand_subword (operands[1], 1, 0, DImode);
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operands[8] = operand_subword (operands[2], 1, 0, DImode);"
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[(set_attr "op_type" "NN")])
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(define_insn_and_split "*subdi3_31"
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[(set (match_operand:DI 0 "register_operand" "=&d")
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(minus:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "general_operand" "do") ) )
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(clobber (reg:CC 33))]
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"!TARGET_64BIT"
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"!TARGET_CPU_ZARCH"
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"#"
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"&& reload_completed"
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[(parallel
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@ -4057,6 +4107,127 @@
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(set_attr "type" "fsimps,fsimps")])
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;;
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;;- Conditional add/subtract instructions.
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;;
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;
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; adddicc instruction pattern(s).
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;
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(define_insn "*adddi3_alc_cc"
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[(set (reg 33)
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(compare
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(plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
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(match_operand:DI 2 "general_operand" "d,m"))
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(match_operand:DI 3 "s390_alc_comparison" ""))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=d,d")
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(plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
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"@
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alcgr\\t%0,%2
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alcg\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*adddi3_alc"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
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(match_operand:DI 2 "general_operand" "d,m"))
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(match_operand:DI 3 "s390_alc_comparison" "")))
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(clobber (reg:CC 33))]
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"TARGET_64BIT"
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"@
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alcgr\\t%0,%2
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alcg\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subdi3_slb_cc"
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[(set (reg 33)
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(compare
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(minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
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(match_operand:DI 2 "general_operand" "d,m"))
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(match_operand:DI 3 "s390_slb_comparison" ""))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=d,d")
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(minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
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"@
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slbgr\\t%0,%2
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slbg\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subdi3_slb"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
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(match_operand:DI 2 "general_operand" "d,m"))
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(match_operand:DI 3 "s390_slb_comparison" "")))
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(clobber (reg:CC 33))]
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"TARGET_64BIT"
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"@
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slbgr\\t%0,%2
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slbg\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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;
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; addsicc instruction pattern(s).
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;
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(define_insn "*addsi3_alc_cc"
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[(set (reg 33)
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(compare
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(plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
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(match_operand:SI 2 "general_operand" "d,m"))
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(match_operand:SI 3 "s390_alc_comparison" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=d,d")
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(plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
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"@
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alcr\\t%0,%2
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alc\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*addsi3_alc"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
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(match_operand:SI 2 "general_operand" "d,m"))
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(match_operand:SI 3 "s390_alc_comparison" "")))
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(clobber (reg:CC 33))]
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"TARGET_CPU_ZARCH"
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"@
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alcr\\t%0,%2
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alc\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subsi3_slb_cc"
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[(set (reg 33)
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(compare
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(minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
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(match_operand:SI 2 "general_operand" "d,m"))
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(match_operand:SI 3 "s390_slb_comparison" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=d,d")
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(minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
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"@
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slbr\\t%0,%2
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slb\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subsi3_slb"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
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(match_operand:SI 2 "general_operand" "d,m"))
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(match_operand:SI 3 "s390_slb_comparison" "")))
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(clobber (reg:CC 33))]
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"TARGET_CPU_ZARCH"
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"@
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slbr\\t%0,%2
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slb\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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;;
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;;- Multiply instructions.
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;;
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Loading…
Add table
Reference in a new issue