Changelog entry:
2012-07-25 Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* common/config/i386/i386-common.c (OPTION_MASK_ISA_PRFCHW_SET): New.
(OPTION_MASK_ISA_PRFCHW_UNSET): Likewise.
(ix86_handle_option): Handle mprfchw option.
* config.gcc (i[34567]86-*-*): Add prfchwintrin.h.
(x86_64-*-*): Likewise.
* config/i386/prfchwintrin.h: New header.
* config/i386/cpuid.h (bit_PRFCHW): New.
(bit_BMI): Formatting fix.
(bit_HLE): Likewise.
(bit_RTM): Likewise.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
PREFETCHW support.
* config/i386/i386-c.c: Define __PRFCHW__ if needed.
* config/i386/i386.c (ix86_target_string): Define
-mprfchw option. Formatting fixes.
(PTA_HLE): Formatting fix.
(PTA_PRFCHW): New.
(ix86_option_override_internal): Handle new option.
(ix86_valid_target_attribute_inner_p): Add OPT_mprfchw.
* config/i386/i386.h (TARGET_PRFCHW): New.
* config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW.
* config/i386/i386.opt (mprfchw): New.
* config/i386/mm3dnow.h: Move _m_prefetchw from here to
prfchwintrin.h.
* config/i386/x86intrin.h: Include prfchwintrin.h.
testsuite/Changelog entry:
2012-07-24 Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gcc.target/i386/prefetchw-1.c: New.
* gcc.target/i386/sse-12.c: Add -mprfchw.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r189844
This commit is contained in:
Kirill Yukhin
Kirill Yukhin
parent
4bd5abcae1
commit
e61c94dd31
22 changed files with 164 additions and 32 deletions
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@ -1,3 +1,32 @@
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2012-07-25 Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* common/config/i386/i386-common.c (OPTION_MASK_ISA_PRFCHW_SET): New.
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(OPTION_MASK_ISA_PRFCHW_UNSET): Likewise.
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(ix86_handle_option): Handle mprfchw option.
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* config.gcc (i[34567]86-*-*): Add prfchwintrin.h.
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(x86_64-*-*): Likewise.
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* config/i386/prfchwintrin.h: New header.
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* config/i386/cpuid.h (bit_PRFCHW): New.
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(bit_BMI): Formatting fix.
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(bit_HLE): Likewise.
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(bit_RTM): Likewise.
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect
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PREFETCHW support.
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* config/i386/i386-c.c: Define __PRFCHW__ if needed.
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* config/i386/i386.c (ix86_target_string): Define
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-mprfchw option. Formatting fixes.
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(PTA_HLE): Formatting fix.
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(PTA_PRFCHW): New.
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(ix86_option_override_internal): Handle new option.
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(ix86_valid_target_attribute_inner_p): Add OPT_mprfchw.
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* config/i386/i386.h (TARGET_PRFCHW): New.
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* config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW.
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* config/i386/i386.opt (mprfchw): New.
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* config/i386/mm3dnow.h: Move _m_prefetchw from here to
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prfchwintrin.h.
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* config/i386/x86intrin.h: Include prfchwintrin.h.
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2012-07-25 Sergey Melnikov <sergey.melnikov@intel.com>
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* config/i386/i386.md (stack_protect_set): Disable the pattern
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@ -55,6 +55,7 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_AVX2_SET \
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(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
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#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
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#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
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/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
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as -msse4.2. */
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@ -123,6 +124,7 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
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#define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
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#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
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#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
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/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
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as -mno-sse4.1. */
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@ -568,6 +570,19 @@ ix86_handle_option (struct gcc_options *opts,
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}
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return true;
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case OPT_mprfchw:
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if (value)
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{
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
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}
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else
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{
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
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}
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return true;
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/* Comes from final.c -- no real reason to change it. */
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#define MAX_CODE_ALIGN 16
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@ -361,7 +361,7 @@ i[34567]86-*-*)
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ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
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lzcntintrin.h bmiintrin.h bmi2intrin.h tbmintrin.h
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avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
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xtestintrin.h"
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xtestintrin.h prfchwintrin.h"
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;;
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x86_64-*-*)
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cpu_type=i386
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@ -375,7 +375,7 @@ x86_64-*-*)
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ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
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lzcntintrin.h bmiintrin.h tbmintrin.h bmi2intrin.h
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avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
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xtestintrin.h"
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xtestintrin.h prfchwintrin.h"
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need_64bit_hwint=yes
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;;
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ia64-*-*)
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@ -65,11 +65,14 @@
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/* Extended Features (%eax == 7) */
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#define bit_FSGSBASE (1 << 0)
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#define bit_BMI (1 << 3)
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#define bit_HLE (1 << 4)
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#define bit_BMI (1 << 3)
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#define bit_HLE (1 << 4)
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#define bit_AVX2 (1 << 5)
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#define bit_BMI2 (1 << 8)
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#define bit_RTM (1 << 11)
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#define bit_PRFCHW (1 << 8)
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#define bit_RTM (1 << 11)
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#define bit_RDSEED (1 << 18)
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#define bit_ADX (1 << 19)
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx may be the PIC register. */
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@ -399,6 +399,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
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unsigned int has_hle = 0, has_rtm = 0;
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unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
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unsigned int has_prfchw = 0;
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bool arch;
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@ -465,6 +466,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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has_avx2 = ebx & bit_AVX2;
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has_bmi2 = ebx & bit_BMI2;
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has_fsgsbase = ebx & bit_FSGSBASE;
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has_prfchw = ecx & bit_PRFCHW;
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}
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/* Check cpuid level of extended features. */
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@ -745,11 +747,12 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
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const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
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const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
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const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
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options = concat (options, cx16, sahf, movbe, ase, pclmul,
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popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
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tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
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hle, rdrnd, f16c, fsgsbase, NULL);
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hle, rdrnd, f16c, fsgsbase, prfchw, NULL);
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}
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done:
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@ -296,6 +296,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__RDRND__");
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if (isa_flag & OPTION_MASK_ISA_F16C)
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def_or_undef (parse_in, "__F16C__");
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if (isa_flag & OPTION_MASK_ISA_PRFCHW)
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def_or_undef (parse_in, "__PRFCHW__");
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if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
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def_or_undef (parse_in, "__SSE_MATH__");
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if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
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@ -2748,7 +2748,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
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preceding options while match those first. */
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static struct ix86_target_opts isa_opts[] =
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{
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{ "-mfma4", OPTION_MASK_ISA_FMA4 },
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{ "-mfma4", OPTION_MASK_ISA_FMA4 },
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{ "-mfma", OPTION_MASK_ISA_FMA },
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{ "-mxop", OPTION_MASK_ISA_XOP },
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{ "-mlwp", OPTION_MASK_ISA_LWP },
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@ -2756,17 +2756,18 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
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{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
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{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
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{ "-mssse3", OPTION_MASK_ISA_SSSE3 },
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{ "-msse3", OPTION_MASK_ISA_SSE3 },
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{ "-msse2", OPTION_MASK_ISA_SSE2 },
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{ "-msse3", OPTION_MASK_ISA_SSE3 },
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{ "-msse2", OPTION_MASK_ISA_SSE2 },
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{ "-msse", OPTION_MASK_ISA_SSE },
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{ "-m3dnow", OPTION_MASK_ISA_3DNOW },
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{ "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
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{ "-mmmx", OPTION_MASK_ISA_MMX },
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{ "-mabm", OPTION_MASK_ISA_ABM },
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{ "-mbmi", OPTION_MASK_ISA_BMI },
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{ "-mbmi2", OPTION_MASK_ISA_BMI2 },
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{ "-mbmi2", OPTION_MASK_ISA_BMI2 },
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{ "-mlzcnt", OPTION_MASK_ISA_LZCNT },
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{ "-mhle", OPTION_MASK_ISA_HLE },
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{ "-mprfchw", OPTION_MASK_ISA_PRFCHW },
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{ "-mtbm", OPTION_MASK_ISA_TBM },
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{ "-mpopcnt", OPTION_MASK_ISA_POPCNT },
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{ "-mmovbe", OPTION_MASK_ISA_MOVBE },
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@ -2775,7 +2776,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
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{ "-mpclmul", OPTION_MASK_ISA_PCLMUL },
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{ "-mfsgsbase", OPTION_MASK_ISA_FSGSBASE },
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{ "-mrdrnd", OPTION_MASK_ISA_RDRND },
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{ "-mf16c", OPTION_MASK_ISA_F16C },
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{ "-mf16c", OPTION_MASK_ISA_F16C },
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{ "-mrtm", OPTION_MASK_ISA_RTM },
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};
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@ -3042,7 +3043,8 @@ ix86_option_override_internal (bool main_args_p)
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#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
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#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
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#define PTA_RTM (HOST_WIDE_INT_1 << 32)
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#define PTA_HLE (HOST_WIDE_INT_1 << 33)
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#define PTA_HLE (HOST_WIDE_INT_1 << 33)
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#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
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/* if this reaches 64, need to widen struct pta flags below */
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static struct pta
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@ -3528,6 +3530,9 @@ ix86_option_override_internal (bool main_args_p)
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if (processor_alias_table[i].flags & PTA_HLE
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&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_HLE))
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ix86_isa_flags |= OPTION_MASK_ISA_HLE;
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if (processor_alias_table[i].flags & PTA_PRFCHW
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&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
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ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
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if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
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x86_prefetch_sse = true;
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@ -3735,10 +3740,11 @@ ix86_option_override_internal (bool main_args_p)
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/* Turn on MMX builtins for -msse. */
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if (TARGET_SSE)
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{
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ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
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x86_prefetch_sse = true;
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}
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ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
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/* Enable SSE prefetch. */
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if (TARGET_SSE || TARGET_PRFCHW)
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x86_prefetch_sse = true;
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/* Turn on popcnt instruction for -msse4.2 or -mabm. */
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if (TARGET_SSE4_2 || TARGET_ABM)
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@ -4348,6 +4354,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
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IX86_ATTR_ISA ("f16c", OPT_mf16c),
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IX86_ATTR_ISA ("rtm", OPT_mrtm),
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IX86_ATTR_ISA ("hle", OPT_mhle),
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IX86_ATTR_ISA ("prfchw", OPT_mprfchw),
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/* enum options */
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IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
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@ -76,6 +76,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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#define TARGET_F16C OPTION_ISA_F16C
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#define TARGET_RTM OPTION_ISA_RTM
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#define TARGET_HLE OPTION_ISA_HLE
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#define TARGET_PRFCHW OPTION_ISA_PRFCHW
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#define TARGET_LP64 OPTION_ABI_64
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#define TARGET_X32 OPTION_ABI_X32
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@ -17626,12 +17626,14 @@
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gcc_assert (locality >= 0 && locality <= 3);
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gcc_assert (GET_MODE (operands[0]) == Pmode
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|| GET_MODE (operands[0]) == VOIDmode);
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if (TARGET_PRFCHW && rw)
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operands[2] = GEN_INT (3);
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/* Use 3dNOW prefetch in case we are asking for write prefetch not
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supported by SSE counterpart or the SSE prefetch is not available
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(K6 machines). Otherwise use SSE prefetch as it allows specifying
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of locality. */
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if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
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else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
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operands[2] = GEN_INT (3);
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else
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operands[1] = const0_rtx;
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@ -17662,7 +17664,7 @@
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[(prefetch (match_operand:P 0 "address_operand" "p")
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(match_operand:SI 1 "const_int_operand" "n")
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(const_int 3))]
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"TARGET_3DNOW"
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"TARGET_3DNOW || TARGET_PRFCHW"
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{
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if (INTVAL (operands[1]) == 0)
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return "prefetch\t%a0";
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@ -532,6 +532,10 @@ mhle
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Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
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Support Hardware Lock Elision prefixes
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mprfchw
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Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
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Support PREFETCHW instruction
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mtbm
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Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
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Support TBM built-in functions and code generation
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@ -30,6 +30,7 @@
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#ifdef __3dNOW__
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#include <mmintrin.h>
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#include <prfchwintrin.h>
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_m_femms (void)
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@ -157,12 +158,6 @@ _m_prefetch (void *__P)
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__builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */);
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}
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_m_prefetchw (void *__P)
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{
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__builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */);
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}
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extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_m_from_float (float __A)
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{
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42
gcc/config/i386/prfchwintrin.h
Normal file
42
gcc/config/i386/prfchwintrin.h
Normal file
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@ -0,0 +1,42 @@
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/* Copyright (C) 2012 Free Software Foundation, Inc.
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This file is part of GCC.
|
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|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#if !defined _X86INTRIN_H_INCLUDED && !defined _MM3DNOW_H_INCLUDED
|
||||
# error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead."
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined (__PRFCHW__) && !defined (__3dNOW__)
|
||||
# error "PRFCHW instruction not enabled"
|
||||
#endif /* __PRFCHW__ or __3dNOW__*/
|
||||
|
||||
#ifndef _PRFCHWINTRIN_H_INCLUDED
|
||||
#define _PRFCHWINTRIN_H_INCLUDED
|
||||
|
||||
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_m_prefetchw (void *__P)
|
||||
{
|
||||
__builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */);
|
||||
}
|
||||
|
||||
#endif /* _PRFCHWINTRIN_H_INCLUDED */
|
||||
|
|
@ -97,4 +97,8 @@
|
|||
#include <popcntintrin.h>
|
||||
#endif
|
||||
|
||||
#ifdef __PRFCHW__
|
||||
#include <prfchwintrin.h>
|
||||
#endif
|
||||
|
||||
#endif /* _X86INTRIN_H_INCLUDED */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,15 @@
|
|||
2012-07-25 Kirill Yukhin <kirill.yukhin@intel.com>
|
||||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||||
|
||||
* gcc.target/i386/prefetchw-1.c: New.
|
||||
* gcc.target/i386/sse-12.c: Add -mprfchw.
|
||||
* gcc.target/i386/sse-13.c: Ditto.
|
||||
* gcc.target/i386/sse-14.c: Ditto.
|
||||
* gcc.target/i386/sse-22.c: Ditto.
|
||||
* gcc.target/i386/sse-23.c: Ditto.
|
||||
* g++.dg/other/i386-2.C: Ditto.
|
||||
* g++.dg/other/i386-3.C: Ditto.
|
||||
|
||||
2012-07-24 Janis Johnson <janisjo@codesourcery.com>
|
||||
|
||||
* lib/gcc-dg.exp (process-message): Don't ignore errors.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
|
||||
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
|
||||
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
|
||||
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
|
||||
|
|
|
|||
13
gcc/testsuite/gcc.target/i386/prefetchw-1.c
Normal file
13
gcc/testsuite/gcc.target/i386/prefetchw-1.c
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mprfchw -O2" } */
|
||||
/* { dg-final { scan-assembler "\[ \\t\]+prefetchw\[ \\t\]+" } } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
void *p;
|
||||
|
||||
void extern
|
||||
prefetchw__test (void)
|
||||
{
|
||||
_m_prefetchw (p);
|
||||
}
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
popcntintrin.h and mm_malloc.h are usable
|
||||
with -O -std=c89 -pedantic-errors. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
|
||||
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
|
||||
|
||||
#ifndef DIFFERENT_PRAGMAS
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm")
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,prfchw")
|
||||
#endif
|
||||
|
||||
/* Following intrinsics require immediate arguments. They
|
||||
|
|
@ -264,7 +264,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
|
|||
|
||||
/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */
|
||||
#ifdef DIFFERENT_PRAGMAS
|
||||
#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma")
|
||||
#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,prfchw")
|
||||
#endif
|
||||
#include <x86intrin.h>
|
||||
/* xopintrin.h */
|
||||
|
|
|
|||
|
|
@ -183,7 +183,7 @@
|
|||
/* rtmintrin.h */
|
||||
#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1)
|
||||
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm")
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,prfchw")
|
||||
#include <wmmintrin.h>
|
||||
#include <smmintrin.h>
|
||||
#include <mm3dnow.h>
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue