sparc.c (sparc_absnegfloat_split_legitimate): New function.
* config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): New function. * config/sparc/sparc.h: Declare it. * config/sparc/sparc.md (float abs/neg splits): Use it. (all other splits): Handle SUBREGs properly where necessary. (unnamed (1<<x)-1 V8PLUS pattern): Disable for now. From-SVN: r21981
This commit is contained in:
David S. Miller
David S. Miller
parent
8e710788f5
commit
e61c29e987
4 changed files with 131 additions and 51 deletions
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@ -1,3 +1,12 @@
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Tue Aug 25 19:17:59 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): New
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function.
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* config/sparc/sparc.h: Declare it.
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* config/sparc/sparc.md (float abs/neg splits): Use it.
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(all other splits): Handle SUBREGs properly where necessary.
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(unnamed (1<<x)-1 V8PLUS pattern): Disable for now.
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Tue Aug 25 19:48:46 1998 Jeffrey A Law (law@cygnus.com)
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* reorg.c (fill_simple_delay_slots): Do not abort if we encounter
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@ -4743,7 +4743,7 @@ order_regs_for_local_alloc ()
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mem<-->reg splits to be run. */
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int
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sparc_splitdi_legitimate(reg, mem)
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sparc_splitdi_legitimate (reg, mem)
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rtx reg;
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rtx mem;
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{
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@ -4767,6 +4767,27 @@ sparc_splitdi_legitimate(reg, mem)
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return 1;
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}
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/* Return 1 if x and y are some kind of REG and they refer to
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different hard registers. This test is guarenteed to be
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run after reload. */
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int
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sparc_absnegfloat_split_legitimate (x, y)
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rtx x, y;
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{
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if (GET_CODE (x) == SUBREG)
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x = alter_subreg (x);
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if (GET_CODE (x) != REG)
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return 0;
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if (GET_CODE (y) == SUBREG)
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y = alter_subreg (y);
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if (GET_CODE (y) != REG)
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return 0;
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if (REGNO (x) == REGNO (y))
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return 0;
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return 1;
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}
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/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
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This makes them candidates for using ldd and std insns.
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@ -3243,6 +3243,7 @@ extern void sparc_emit_set_const32 ();
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extern void sparc_emit_set_const64 ();
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extern void sparc_emit_set_symbolic_const64 ();
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extern int sparc_splitdi_legitimate ();
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extern int sparc_absnegfloat_split_legitimate ();
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extern char *output_cbranch ();
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extern char *output_return ();
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@ -2785,8 +2785,8 @@
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[(set (match_operand:SF 0 "register_operand" "")
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(match_operand:SF 1 "const_double_operand" ""))]
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"TARGET_FPU
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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&& (GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)"
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[(set (match_dup 0) (unspec:SF [(match_dup 1)] 12))
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(set (match_dup 0) (unspec:SF [(match_dup 0) (match_dup 1)] 17))]
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"
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@ -2906,8 +2906,8 @@
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(match_operand:DF 1 "const_double_operand" ""))]
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"TARGET_FPU
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32
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&& (GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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&& reload_completed"
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[(clobber (const_int 0))]
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"
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@ -2917,6 +2917,8 @@
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REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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REAL_VALUE_TO_TARGET_DOUBLE (r, l);
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
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emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
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@ -3096,8 +3098,11 @@
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(match_operand:DF 1 "register_operand" ""))]
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"(! TARGET_V9
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|| (! TARGET_ARCH64
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32))
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))))
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&& reload_completed"
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[(clobber (const_int 0))]
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"
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@ -3137,8 +3142,11 @@
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(match_operand:DF 1 "memory_operand" ""))]
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"((! TARGET_V9
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|| (! TARGET_ARCH64
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32))
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))))
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&& (reload_completed
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&& (((REGNO (operands[0])) % 2) != 0
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|| ! mem_min_alignment (operands[1], 8))
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@ -3179,8 +3187,11 @@
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(match_operand:DF 1 "register_operand" ""))]
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"((! TARGET_V9
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|| (! TARGET_ARCH64
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[1]) < 32))
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&& ((GET_CODE (operands[1]) == REG
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&& REGNO (operands[1]) < 32)
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|| (GET_CODE (operands[1]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[1])) == REG
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&& REGNO (SUBREG_REG (operands[1])) < 32))))
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&& (reload_completed
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&& (((REGNO (operands[1])) % 2) != 0
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|| ! mem_min_alignment (operands[0], 8))
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@ -5666,12 +5677,17 @@
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(match_operand:DI 3 "arith_double_operand" "")]))]
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"! TARGET_ARCH64
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&& reload_completed
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
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(set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
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"
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{
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[4] = gen_highpart (SImode, operands[0]);
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operands[5] = gen_lowpart (SImode, operands[0]);
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operands[6] = gen_highpart (SImode, operands[2]);
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@ -5705,11 +5721,16 @@
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(match_operand:DI 2 "register_operand" "")))]
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"! TARGET_ARCH64
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&& reload_completed
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
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(set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
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"operands[3] = gen_highpart (SImode, operands[0]);
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[6] = gen_lowpart (SImode, operands[0]);
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@ -5810,11 +5831,16 @@
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(match_operand:DI 2 "register_operand" "")))]
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"! TARGET_ARCH64
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&& reload_completed
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
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(set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
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"operands[3] = gen_highpart (SImode, operands[0]);
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[6] = gen_lowpart (SImode, operands[0]);
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@ -5942,11 +5968,16 @@
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(match_operand:DI 2 "register_operand" ""))))]
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"! TARGET_ARCH64
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&& reload_completed
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
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(set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
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"operands[3] = gen_highpart (SImode, operands[0]);
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[6] = gen_lowpart (SImode, operands[0]);
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@ -6275,11 +6306,16 @@
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(not:DI (match_operand:DI 1 "register_operand" "")))]
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"! TARGET_ARCH64
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&& reload_completed
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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&& ((GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32)
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|| (GET_CODE (operands[0]) == SUBREG
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&& GET_CODE (SUBREG_REG (operands[0])) == REG
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
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(set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
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"operands[2] = gen_highpart (SImode, operands[0]);
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[2] = gen_highpart (SImode, operands[0]);
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operands[3] = gen_highpart (SImode, operands[1]);
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operands[4] = gen_lowpart (SImode, operands[0]);
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operands[5] = gen_lowpart (SImode, operands[1]);")
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@ -6526,14 +6562,16 @@
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(neg:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_FPU
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&& ! TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])
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&& reload_completed"
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[(set (match_dup 2) (neg:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))
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(set (match_dup 6) (match_dup 7))]
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
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@ -6556,13 +6594,15 @@
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(neg:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_FPU
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&& TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])
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&& reload_completed"
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[(set (match_dup 2) (neg:DF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
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operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
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@ -6588,13 +6628,15 @@
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(neg:DF (match_operand:DF 1 "register_operand" "")))]
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"TARGET_FPU
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&& ! TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])
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&& reload_completed"
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[(set (match_dup 2) (neg:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
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@ -6637,14 +6679,16 @@
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(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
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"TARGET_FPU
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&& ! TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])
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&& reload_completed"
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[(set (match_dup 2) (abs:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))
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(set (match_dup 6) (match_dup 7))]
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
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@ -6667,13 +6711,15 @@
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(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
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"TARGET_FPU
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&& TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])
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&& reload_completed"
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[(set (match_dup 2) (abs:DF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
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operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
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@ -6699,13 +6745,15 @@
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|||
(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
|
||||
"TARGET_FPU
|
||||
&& ! TARGET_V9
|
||||
&& GET_CODE (operands[0]) == REG
|
||||
&& GET_CODE (operands[1]) == REG
|
||||
&& REGNO (operands[0]) != REGNO (operands[1])
|
||||
&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])
|
||||
&& reload_completed"
|
||||
[(set (match_dup 2) (abs:SF (match_dup 3)))
|
||||
(set (match_dup 4) (match_dup 5))]
|
||||
"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
|
||||
"if (GET_CODE (operands[0]) == SUBREG)
|
||||
operands[0] = alter_subreg (operands[0]);
|
||||
if (GET_CODE (operands[1]) == SUBREG)
|
||||
operands[1] = alter_subreg (operands[1]);
|
||||
operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
|
||||
operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
|
||||
operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
|
||||
operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
|
||||
|
|
@ -6811,13 +6859,14 @@
|
|||
[(set_attr "length" "5,5,6")])
|
||||
|
||||
;; Optimize (1LL<<x)-1
|
||||
;; XXX
|
||||
;; XXX this also needs to be fixed to handle equal subregs
|
||||
;; XXX first before we could re-enable it.
|
||||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "register_operand" "=h")
|
||||
(plus:DI (ashift:DI (const_int 1)
|
||||
(match_operand:SI 2 "arith_operand" "rI"))
|
||||
(const_int -1)))]
|
||||
"TARGET_V8PLUS"
|
||||
"0 && TARGET_V8PLUS"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[2]) == REG && REGNO (operands[2]) == REGNO (operands[0]))
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue